{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,5]],"date-time":"2026-01-05T11:13:05Z","timestamp":1767611585653,"version":"3.37.3"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100006477","name":"Intelligent & Sustainable Medical Electronics Research Fund of National Taiwan University","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100006477","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004663","name":"Ministry of Science and Technology, Taipei, Taiwan","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100004663","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,7]]},"DOI":"10.1109\/tvlsi.2022.3170325","type":"journal-article","created":{"date-parts":[[2022,5,5]],"date-time":"2022-05-05T20:00:40Z","timestamp":1651780840000},"page":"905-914","source":"Crossref","is-referenced-by-count":13,"title":["A 0.0067-mm<sup>2<\/sup> 12-bit 20-MS\/s SAR ADC Using Digital Place-and-Route Tools in 40-nm CMOS"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5312-1875","authenticated-orcid":false,"given":"Yao-Hung","family":"Tsai","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3765-2948","authenticated-orcid":false,"given":"Shen-Iuan","family":"Liu","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2581177"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2720629"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2022.3147954"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3074039"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2018.2856103"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3079406"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2018.2825400"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2938450"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2021.105253"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3078689"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3121245"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3087660"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2609849"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899738"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2865404"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2685463"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2915365"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2822811"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3122027"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780194"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3105028"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2143870"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878830"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231328"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2784761"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/4.760369"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2020.3036143"},{"volume-title":"Cadence Abstract Generator User Guide","year":"2004","key":"ref28"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2418155"},{"volume-title":"Calibre Verification User\u2019s Manual","year":"2002","key":"ref30"},{"volume-title":"Encounter User Guide","year":"2005","key":"ref31"},{"volume-title":"Virtuoso NC-Verilog Environment User Guide","year":"2021","key":"ref32"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2946215"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9809833\/09769748.pdf?arnumber=9769748","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,22]],"date-time":"2024-01-22T22:45:43Z","timestamp":1705963543000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9769748\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7]]},"references-count":33,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3170325","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2022,7]]}}}