{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T16:40:18Z","timestamp":1764175218862,"version":"3.37.3"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,7,1]],"date-time":"2022-07-01T00:00:00Z","timestamp":1656633600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,7]]},"DOI":"10.1109\/tvlsi.2022.3171810","type":"journal-article","created":{"date-parts":[[2022,5,18]],"date-time":"2022-05-18T19:34:44Z","timestamp":1652902484000},"page":"938-951","source":"Crossref","is-referenced-by-count":21,"title":["Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches"],"prefix":"10.1109","volume":"30","author":[{"given":"Kerem","family":"Arikan","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronic Engineering, TOBB University of Economics and Technology, Ankara, Turkey"}]},{"given":"Alessandro","family":"Palumbo","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Ingegneria dell’Informazione, Università degli Studi di Roma Tor Vergata, Rome, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3824-7714","authenticated-orcid":false,"given":"Luca","family":"Cassano","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Milan, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2540-5234","authenticated-orcid":false,"given":"Pedro","family":"Reviriego","sequence":"additional","affiliation":[{"name":"Departamento de Ingeniería Telemática, Universidad Carlos III de Madrid, Madrid, Spain"}]},{"given":"Salvatore","family":"Pontarelli","sequence":"additional","affiliation":[{"name":"Dipartimento di Informatica, Università di Roma La Sapienza, Rome, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7277-7423","authenticated-orcid":false,"given":"Giuseppe","family":"Bianchi","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Ingegneria dell’Informazione, CNIT (Consorzio Nazionale Iteruniversitario per le Telecomunicazioni), Università degli Studi di Roma Tor Vergata, Rome, Italy"}]},{"given":"Oguz","family":"Ergin","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering, TOBB University of Economics and Technology, Ankara, Turkey"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5064-7342","authenticated-orcid":false,"given":"Marco","family":"Ottavi","sequence":"additional","affiliation":[{"name":"Dipartimento di Elettronica, Ingegneria dell’Informazione, CNIT (Consorzio Nazionale Iteruniversitario per le Telecomunicazioni), Università degli Studi di Roma Tor Vergata, Rome, Italy"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSP.2018.8631825"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-017-0031-0"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-32824-9_14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2017.2779824"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.3390\/electronics6030052"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2019.00002"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s41635-017-0025-y"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04138-9_1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-04138-9_2"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2009.19"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.14722\/ndss.2015.23264"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/2976749.2978324"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCC.2014.2358236"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2508859.2516741"},{"key":"ref15","first-page":"189","article-title":"STEALTHMEM: System-level protection against cache-based side channel attacks in the cloud","volume-title":"Proc. 21st USENIX Secur. Symp. (USENIX Secur.)","author":"Kim"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1655008.1655019"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798277"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.jalgor.2003.12.001"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FPL50879.2020.00022"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS48698.2020.9080961"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/DFT52944.2021.9568291"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1007\/11967668_18"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-32946-3_23"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2011.22"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1145\/1314466.1314469"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1229285.1266999"},{"key":"ref27","article-title":"Processor hardware security vulnerabilities and their detection by unique program execution checking","author":"Rahmani Fadiheh","year":"2018","journal-title":"arXiv:1812.04975"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853210"},{"key":"ref29","first-page":"441","article-title":"Micro-architectural cache side-channel attacks and countermeasures","volume-title":"Proc. 26th Asia South Pacific Des. Automat. Conf.","author":"Shen"},{"article-title":"FLUSH+RELOAD: A high resolution, low noise, L3 cache side-channel attack","volume-title":"Proc. 23rd USENIX Secur. Symp. (USENIX Secur.)","author":"Yarom","key":"ref30"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2018.00042"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3058551"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304020"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358273"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_9"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/11605805_1"},{"key":"ref37","article-title":"Cache missing for fun and profit","author":"Percival","year":"2005","journal-title":"Proc. BSDCan"},{"volume-title":"Partitioned cache architecture as a side-channel defense mechanism","year":"2005","author":"Page","key":"ref38"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/1250662.1250723"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1016\/j.asoc.2016.09.014"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS50870.2020.9159708"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD50377.2020.00111"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1145\/3386263.3407586"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9809833\/09777885.pdf?arnumber=9777885","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,22]],"date-time":"2024-01-22T21:49:32Z","timestamp":1705960172000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9777885\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,7]]},"references-count":43,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3171810","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2022,7]]}}}