{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:43Z","timestamp":1740133303136,"version":"3.37.3"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100007812","name":"NASA SBIR Phase-I Research Grant at the University of Washington through Industry Partner KalScott Engineering Inc","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100007812","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,9]]},"DOI":"10.1109\/tvlsi.2022.3184245","type":"journal-article","created":{"date-parts":[[2022,6,23]],"date-time":"2022-06-23T19:33:49Z","timestamp":1656012829000},"page":"1294-1305","source":"Crossref","is-referenced-by-count":0,"title":["A New Pathway Toward Implementing a Fully Integrated Band-Switchable CMOS Power Amplifier Utilizing Bit Optimized Reconfigurable Network (BORN)"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1432-9766","authenticated-orcid":false,"given":"Seyyed Babak","family":"Hamidi","sequence":"first","affiliation":[{"name":"School of Engineering and Technology, University of Washington, Tacoma, WA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0107-5763","authenticated-orcid":false,"given":"Debasis","family":"Dawn","sequence":"additional","affiliation":[{"name":"School of Engineering and Technology, University of Washington, Tacoma, WA, USA"}]}],"member":"263","reference":[{"volume-title":"RF Microelectronics","year":"2012","author":"Razavi","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/APS.2016.7696214"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2016.2530418"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CTTE.2017.8260928"},{"volume-title":"Leading the World Toward a 5G Future","year":"2021","key":"ref5"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.5465\/ambpp.2017.11281abstract"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.3390\/electronics7110271"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2011.2175235"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/WAMICON.2017.7930263"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2009.5357277"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s10470-020-01777-9"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2016.7508299"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IMWS.2010.5441012"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2407775"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2012.2201744"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2011.2152384"},{"article-title":"Bit optimized reconfigurable network (BORN): A new pathway towards implementing a fully integrated band-switchable CMOS power amplifier","year":"2020","author":"Hamidi","key":"ref17"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/WAMICON47156.2021.9443591"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICSICT.2010.5667403"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2005.860894"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.2528\/PIERC09100105"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2008.4561529"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2010.5477353"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.907201"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1590\/0001-3765201620150123"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2620559"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3022908"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2019.2955602"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC.2017.7969085"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1049\/iet-map.2015.0783"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/APCAP.2017.8420526"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MWSYM.2005.1516691"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9874436\/09805676.pdf?arnumber=9805676","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T03:40:09Z","timestamp":1706758809000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9805676\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,9]]},"references-count":32,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3184245","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2022,9]]}}}