{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,7]],"date-time":"2026-03-07T02:44:30Z","timestamp":1772851470534,"version":"3.50.1"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2022,10,1]],"date-time":"2022-10-01T00:00:00Z","timestamp":1664582400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,10,1]],"date-time":"2022-10-01T00:00:00Z","timestamp":1664582400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,10,1]],"date-time":"2022-10-01T00:00:00Z","timestamp":1664582400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61674122"],"award-info":[{"award-number":["61674122"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,10]]},"DOI":"10.1109\/tvlsi.2022.3200946","type":"journal-article","created":{"date-parts":[[2022,8,30]],"date-time":"2022-08-30T19:51:27Z","timestamp":1661889087000},"page":"1391-1400","source":"Crossref","is-referenced-by-count":12,"title":["A 12-Bit Current-Steering DAC With Unary- Splitting -Binary Segmented Architecture and Improved Decoding Circuit Topology"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0697-1049","authenticated-orcid":false,"given":"Xingyuan","family":"Tong","sequence":"first","affiliation":[{"name":"School of Electronics Engineering, Xi’an University of Posts and Telecommunications, Xi’an, China"}]},{"given":"Dong","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Xi’an University of Posts and Telecommunications, Xi’an, China"}]},{"given":"Ronghua","family":"Wang","sequence":"additional","affiliation":[{"name":"TOLL Microelectronics, Xi’an, China"}]}],"member":"263","reference":[{"key":"ref1","first-page":"116","article-title":"A 12-b 500-MS\/s DAC with >70 dB SFDR up to 120 MHz in 0.18\u03bcmCMOS","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Dorris"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2164302"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2866819"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2503727"},{"issue":"2","key":"ref5","doi-asserted-by":"crossref","first-page":"444","DOI":"10.1109\/JSSC.2011.2168651","article-title":"A 10 bit, 500 MSample\/s CMOS DAC in 0.6 mm2","volume":"47","author":"Lin","year":"1998","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/cje.2019.10.002"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2019.104662"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2399971"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2017.2689518"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1986.1052639"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IranianCEE.2016.7585835"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/4.910469"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385752"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2386332"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2791462"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2866819"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3085587"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2404222"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9904512\/09870692.pdf?arnumber=9870692","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T12:43:22Z","timestamp":1706791402000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9870692\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10]]},"references-count":19,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3200946","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,10]]}}}