{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,23]],"date-time":"2026-01-23T13:46:47Z","timestamp":1769176007105,"version":"3.49.0"},"reference-count":50,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,11,1]],"date-time":"2022-11-01T00:00:00Z","timestamp":1667260800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,11]]},"DOI":"10.1109\/tvlsi.2022.3203307","type":"journal-article","created":{"date-parts":[[2022,9,19]],"date-time":"2022-09-19T20:08:56Z","timestamp":1663618136000},"page":"1705-1715","source":"Crossref","is-referenced-by-count":8,"title":["Design and Implementation of a Secure RISC-V Microprocessor"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3387-054X","authenticated-orcid":false,"given":"Kleber","family":"Stangherlin","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering (ECE) Department, University of Waterloo, Waterloo, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8256-9828","authenticated-orcid":false,"given":"Manoj","family":"Sachdev","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering (ECE) Department, University of Waterloo, Waterloo, Canada"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Efficient shift registers, LFSR counters, and long pseudo random sequence generators","author":"Alfke","year":"1996"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2320154"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2625341"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.6028\/nist.sp.800-22r1a"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9089-3"},{"key":"ref6","volume-title":"Test vector leakage assessment (TVLA) methodology in practice","author":"Becker","year":"2013"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2861738"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-75208-2_2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/11894063_19"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/BF00993091"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2840049"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3323485"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415649"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3113335"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48059-5_15"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-24837-0_5"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2018.i2.1-21"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-54669-8_6"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-66787-4_6"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-018-0184-y"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/2996366.2996426"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3338467.3358950"},{"key":"ref23","first-page":"495","article-title":"Securing computer hardware using 3d integrated circuit (IC) technology and split manufacturing for obfuscation","volume-title":"Proc. USENIX Secur. Symp.","author":"Imeson"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45146-4_27"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3070687"},{"key":"ref26","volume-title":"A proposal for: Functionality classes for random number generators, version 2.0","author":"Killmann","year":"2011"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3052146"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960482"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30574-3_24"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2558490"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2014.2342034"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/11935308_38"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_6"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/11545262_13"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-45418-7_17"},{"key":"ref37","volume-title":"Digital Integrated Circuits","volume":"2","author":"Rabaey","year":"2002"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-47989-6_37"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.3233\/ida-2007-11508"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2875112"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_21"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3203307"},{"key":"ref43","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","volume-title":"Proc. E-SSCC","author":"Tiri"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/date.2004.1268856"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36400-5_32"},{"key":"ref46","volume-title":"Combinational logic design for AES subbyte transformation on masked data","author":"Trichina","year":"2003"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19074-2_8"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1016\/0196-8858(86)90028-X"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2016.2519383"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3137312"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9925603\/09895198.pdf?arnumber=9895198","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,24]],"date-time":"2024-01-24T02:45:13Z","timestamp":1706064313000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9895198\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11]]},"references-count":50,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3203307","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,11]]}}}