{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,31]],"date-time":"2026-01-31T03:12:28Z","timestamp":1769829148760,"version":"3.49.0"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,12,1]],"date-time":"2022-12-01T00:00:00Z","timestamp":1669852800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China (NSFC) under Key Program","doi-asserted-by":"publisher","award":["62034007"],"award-info":[{"award-number":["62034007"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Key-Area Research and Development Program of Guangdong Province","award":["2019B010116002"],"award-info":[{"award-number":["2019B010116002"]}]},{"DOI":"10.13039\/501100021171","name":"Basic and Applied Basic Research Foundation of Guangdong Province","doi-asserted-by":"publisher","award":["2019B1515120024"],"award-info":[{"award-number":["2019B1515120024"]}],"id":[{"id":"10.13039\/501100021171","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Shenzhen Science and Technology Program","award":["KQTD20200820113051096"],"award-info":[{"award-number":["KQTD20200820113051096"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2022,12]]},"DOI":"10.1109\/tvlsi.2022.3210069","type":"journal-article","created":{"date-parts":[[2022,11,3]],"date-time":"2022-11-03T21:02:11Z","timestamp":1667509331000},"page":"1878-1890","source":"Crossref","is-referenced-by-count":20,"title":["An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks"],"prefix":"10.1109","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2527-6778","authenticated-orcid":false,"given":"Wei","family":"Mao","sequence":"first","affiliation":[{"name":"School of Microelectronics and the Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Liuyao","family":"Dai","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Engineering, University of California at Merced, Merced, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3251-931X","authenticated-orcid":false,"given":"Kai","family":"Li","sequence":"additional","affiliation":[{"name":"School of Microelectronics and the Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Quan","family":"Cheng","sequence":"additional","affiliation":[{"name":"Department of Communications and Computer Engineering, Kyoto University, Kyoto, Japan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuhang","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3119-3805","authenticated-orcid":false,"given":"Laimin","family":"Du","sequence":"additional","affiliation":[{"name":"School of Microelectronics and the Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaobo","family":"Luo","sequence":"additional","affiliation":[{"name":"School of Microelectronics and the Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7794-3985","authenticated-orcid":false,"given":"Mingqiang","family":"Huang","sequence":"additional","affiliation":[{"name":"Shenzhen Institute of Advanced Technology, Chinese Academy of Sciences, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2674-4118","authenticated-orcid":false,"given":"Hao","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Microelectronics and the Engineering Research Center of Integrated Circuits for Next-Generation Communications, Ministry of Education, Southern University of Science and Technology, Shenzhen, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref32","first-page":"246","article-title":"Envision: A 0.26-to-10 TOPS\/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI","author":"moons","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/N-SSC.2007.4785543"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2017.8335698"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2865489"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00069"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3316781.3317784"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218656"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS.2019.8771481"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724440"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3128435"},{"key":"ref17","first-page":"6869","article-title":"Quantized neural networks: Training neural networks with low precision weights and activations","volume":"18","author":"hubara","year":"2016","journal-title":"J Mach Learn Res"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00826"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774679"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2985963"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2019.01099"},{"key":"ref27","first-page":"9099","article-title":"Transformer quality in linear time","author":"hua","year":"2022","journal-title":"Proc 39th Int Conf Mach Learn (ICML)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2019.00881"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD45719.2019.8942147"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2001269.2001291"},{"key":"ref5","first-page":"1997","article-title":"Neural architecture search: A survey","volume":"20","author":"elsken","year":"2019","journal-title":"J Mach Learn Res"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2950386"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2020.3034041"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2018.2808319"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2016.2597140"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0059-3"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1038\/s42256-019-0134-0"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2881913"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3386263.3407582"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415644"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2019.2926275"},{"key":"ref25","first-page":"1","article-title":"Mixed precision quantization of convnets via differentiable neural architecture search","author":"wu","year":"2019","journal-title":"Proc Int Conf Learn Represent (ICLR)"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9975838\/09920733.pdf?arnumber=9920733","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,12,26]],"date-time":"2022-12-26T19:16:27Z","timestamp":1672082187000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9920733\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,12]]},"references-count":32,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3210069","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,12]]}}}