{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T10:21:46Z","timestamp":1740133306865,"version":"3.37.3"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,1,1]],"date-time":"2023-01-01T00:00:00Z","timestamp":1672531200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"NSF of China","doi-asserted-by":"publisher","award":["62171313","61974102"],"award-info":[{"award-number":["62171313","61974102"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"ACHILLES"},{"DOI":"10.13039\/501100011033","name":"Agencia Estatal de Investigaci\u00f3n","doi-asserted-by":"publisher","award":["PID2019-104207RB-I00"],"award-info":[{"award-number":["PID2019-104207RB-I00"]}],"id":[{"id":"10.13039\/501100011033","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2023,1]]},"DOI":"10.1109\/tvlsi.2022.3224137","type":"journal-article","created":{"date-parts":[[2022,12,2]],"date-time":"2022-12-02T20:58:30Z","timestamp":1670014710000},"page":"142-146","source":"Crossref","is-referenced-by-count":1,"title":["Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders"],"prefix":"10.1109","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9887-1418","authenticated-orcid":false,"given":"Zhen","family":"Gao","sequence":"first","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin International Engineering Institute and School of Microelectronics, respectively, Tianjin University, Tianjin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinchang","family":"Shi","sequence":"additional","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin International Engineering Institute and School of Microelectronics, respectively, Tianjin University, Tianjin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1375-0508","authenticated-orcid":false,"given":"Qiang","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Electrical and Information Engineering, Tianjin International Engineering Institute and School of Microelectronics, respectively, Tianjin University, Tianjin, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4770-4967","authenticated-orcid":false,"given":"Anees","family":"Ullah","sequence":"additional","affiliation":[{"name":"Department of Electronics Engineering, University of Engineering and Technology, Peshawar, Abbottabad, Pakistan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2540-5234","authenticated-orcid":false,"given":"Pedro","family":"Reviriego","sequence":"additional","affiliation":[{"name":"Departamento de Ingener&#x00ED;a de Sistemas Telem&#x00E1;ticos, Universidad Polit&#x00E9;cnica de Madrid, Madrid, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s10623-012-9628-z"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2005.1415905"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISIT.2008.4595149"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/(SICI)1097-024X(199709)27:9<995::AID-SPE111>3.0.CO;2-6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2019.8594798"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MSPEC.2018.8362213"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/5.90113"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2017.2713445"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TAES.2016.140914"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-31069-5"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/SPIN.2016.7566730"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.899241"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3066804"},{"volume-title":"Computational method and apparatus for finite field arithmetic","year":"1986","author":"Omura","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/LCOMM.2004.833807"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.24"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2018.2812719"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/9998453\/09969170.pdf?arnumber=9969170","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T02:50:38Z","timestamp":1706755838000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9969170\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,1]]},"references-count":17,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3224137","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2023,1]]}}}