{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T20:21:13Z","timestamp":1771705273458,"version":"3.50.1"},"reference-count":38,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,3,1]],"date-time":"2023-03-01T00:00:00Z","timestamp":1677628800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000185","name":"DARPA ERI 3DSOC Program","doi-asserted-by":"publisher","award":["HR001118C0096"],"award-info":[{"award-number":["HR001118C0096"]}],"id":[{"id":"10.13039\/100000185","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1908045"],"award-info":[{"award-number":["CCF-1908045"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2023,3]]},"DOI":"10.1109\/tvlsi.2022.3228850","type":"journal-article","created":{"date-parts":[[2023,1,17]],"date-time":"2023-01-17T18:45:24Z","timestamp":1673981124000},"page":"296-309","source":"Crossref","is-referenced-by-count":10,"title":["Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs"],"prefix":"10.1109","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9353-6397","authenticated-orcid":false,"given":"Arjun","family":"Chaudhuri","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sanmitra","family":"Banerjee","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4380-6656","authenticated-orcid":false,"given":"Jinwoo","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung Kyu","family":"Lim","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4475-6435","authenticated-orcid":false,"given":"Krishnendu","family":"Chakrabarty","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Duke University, Durham, NC, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2942982"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938045"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720534"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2015.1111"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2864290"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3041026"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614653"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1063\/1.1931152"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2019.8791515"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3464430"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294793"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/S3S.2015.7333529"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223698"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2019.00096"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3372780.3375567"},{"key":"ref16","first-page":"805","article-title":"Design automation and testing of monolithic 3D ICs: Opportunities, challenges, and solutions","volume-title":"Proc. ICCAD","author":"Chang"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1149\/06405.0381ecst"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1063\/1.4948890"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/EPEPS.2016.7835425"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046211"},{"key":"ref21","volume-title":"Method of forming a self-aligned copper diffusion barrier in vias","author":"Geffken","year":"1999"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/3DIC.2009.5306569"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/43.945309"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2013.6651894"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICMEL.2004.1314941"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2015.7116296"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2021.3106415"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116293"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1371\/journal.pone.0221043"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3063651"},{"key":"ref31","volume-title":"Testing monolithic three dimensional integrated circuits","author":"Kannan","year":"2020"},{"key":"ref32","volume-title":"DEF Syntax","year":"2022"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/66.56568"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/43.127625"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/66.705378"},{"issue":"1","key":"ref36","first-page":"6","article-title":"A study of sufficient conditions for Hamiltonian cycles","volume":"1","author":"DeLeon","year":"2000","journal-title":"Rose-Hulman Undergraduate Math. J."},{"key":"ref37","volume-title":"Combinatorial Optimization: Polyhedra and Efficiency","volume":"24","author":"Schrijver","year":"2003"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/322186.322187"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/10049803\/10018839-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10049803\/10018839.pdf?arnumber=10018839","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,13]],"date-time":"2024-02-13T07:23:09Z","timestamp":1707808989000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10018839\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,3]]},"references-count":38,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3228850","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,3]]}}}