{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T18:51:15Z","timestamp":1771613475189,"version":"3.50.1"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Science and Technology Development Fund, Macau, SAR","award":["FDCT 0024\/2021\/A"],"award-info":[{"award-number":["FDCT 0024\/2021\/A"]}]},{"name":"Science and Technology Development Fund, Macau, SAR","award":["FDCT 0036\/2020\/AGJ"],"award-info":[{"award-number":["FDCT 0036\/2020\/AGJ"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1109\/tvlsi.2022.3229342","type":"journal-article","created":{"date-parts":[[2022,12,23]],"date-time":"2022-12-23T18:38:59Z","timestamp":1671820739000},"page":"188-198","source":"Crossref","is-referenced-by-count":12,"title":["A 3.6-GHz Type-II Sampling PLL With a Differential Parallel-Series Double-Edge S-PD Scoring 43.1-fs<sub>RMS<\/sub>Jitter, \u2212258.7-dB FOM, and \u221275.17-dBc Reference Spur"],"prefix":"10.1109","volume":"31","author":[{"given":"Yunbo","family":"Huang","sequence":"first","affiliation":[{"name":"State-Key Laboratory of Analog and Mixed-Signal VLSI and IME\/ECE-FST, University of Macau, Macau, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2794-1324","authenticated-orcid":false,"given":"Yong","family":"Chen","sequence":"additional","affiliation":[{"name":"State-Key Laboratory of Analog and Mixed-Signal VLSI and IME\/ECE-FST, University of Macau, Macau, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3462-6952","authenticated-orcid":false,"given":"Bo","family":"Zhao","sequence":"additional","affiliation":[{"name":"Institute of VLSI Design, Zhejiang University, Hangzhou, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3579-8740","authenticated-orcid":false,"given":"Pui-In","family":"Mak","sequence":"additional","affiliation":[{"name":"State-Key Laboratory of Analog and Mixed-Signal VLSI and IME\/ECE-FST, University of Macau, Macau, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2821-648X","authenticated-orcid":false,"given":"Rui P.","family":"Martins","sequence":"additional","affiliation":[{"name":"State-Key Laboratory of Analog and Mixed-Signal VLSI and IME\/ECE-FST, University of Macau, Macau, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3057580"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2018.8310342"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2874013"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662364"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2951377"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2967562"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/esscirc53450.2021.9567834"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3131219"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3106237"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3105335"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731578"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492419"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2889690"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3089930"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3123827"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3031901"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2619362"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2017.7870392"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2018.8310336"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2941259"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3065462"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2511157"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3049365"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3029016"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3094934"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3033271"},{"key":"ref27","article-title":"CMOS signal synthesizers for emerging RF-to-optical applications","author":"Sharma","year":"2018"},{"key":"ref28","volume-title":"RF Microelectronics","author":"Razavi","year":"2012"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3180351"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2018.2851499"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662470"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3013259"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/rfic49505.2020.9218290"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3096196"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365761"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401557"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2886321"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2728781"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2951384"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2959513"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365775"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10019332\/09998487.pdf?arnumber=9998487","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T12:43:38Z","timestamp":1709383418000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9998487\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2]]},"references-count":41,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3229342","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,2]]}}}