{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:13:13Z","timestamp":1781885593292,"version":"3.54.5"},"reference-count":64,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,2,1]],"date-time":"2023-02-01T00:00:00Z","timestamp":1675209600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research and Development Program through the National Research Foundation of Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100014188","name":"Ministry of Science and ICT, South Korea","doi-asserted-by":"publisher","award":["2020M3H2A1078045"],"award-info":[{"award-number":["2020M3H2A1078045"]}],"id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"Basic Science Research Program through the National Research Foundation of Korea","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100010002","name":"Ministry of Education","doi-asserted-by":"publisher","award":["2022R1I1A3073214"],"award-info":[{"award-number":["2022R1I1A3073214"]}],"id":[{"id":"10.13039\/100010002","id-type":"DOI","asserted-by":"publisher"}]},{"name":"BK21 FOUR Project"},{"name":"Ministry of Education, Korea","award":["4199990113966"],"award-info":[{"award-number":["4199990113966"]}]},{"DOI":"10.13039\/100004358","name":"Samsung Electronics Company Ltd","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2023,2]]},"DOI":"10.1109\/tvlsi.2022.3229442","type":"journal-article","created":{"date-parts":[[2022,12,23]],"date-time":"2022-12-23T18:38:59Z","timestamp":1671820739000},"page":"163-176","source":"Crossref","is-referenced-by-count":20,"title":["NS3K: A 3-nm Nanosheet FET Standard Cell Library Development and its Impact"],"prefix":"10.1109","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0878-8600","authenticated-orcid":false,"given":"Taehak","family":"Kim","sequence":"first","affiliation":[{"name":"School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8960-6954","authenticated-orcid":false,"given":"Jaehoon","family":"Jeong","sequence":"additional","affiliation":[{"name":"School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Seungmin","family":"Woo","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9969-2307","authenticated-orcid":false,"given":"Jeonggyu","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hyunwoo","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ahyeon","family":"Nam","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Changdong","family":"Lee","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jinmin","family":"Seo","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Minji","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Siwon","family":"Ryu","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4059-4662","authenticated-orcid":false,"given":"Yoonju","family":"Oh","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5243-4132","authenticated-orcid":false,"given":"Taigon","family":"Song","sequence":"additional","affiliation":[{"name":"School of Electronic and Electrical Engineering, Kyungpook National University (KNU), Daegu, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2017.7998183"},{"key":"ref2","first-page":"28","article-title":"3 nm GAA technology featuring multi-bridge-channel FET for low power and high performance applications","author":"Bae","year":"2018","journal-title":"IEDM Tech. Dig."},{"key":"ref3","volume-title":"International Roadmap for Device and Systems","year":"2018"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/vlsit.2018.8510683"},{"key":"ref5","first-page":"20","article-title":"Power aware FinFET and lateral nanosheet FET targeting for 3 nm CMOS technology","author":"Yakimets","year":"2017","journal-title":"IEDM Tech. Dig."},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5654225"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2016.2572144"},{"key":"ref8","first-page":"89","article-title":"DTCO exploration for efficient standard cell power rails","volume-title":"Proc. SPIE","volume":"10588","author":"Chava"},{"key":"ref9","first-page":"19","article-title":"Buried power rails and back-side power grids: Arm CPU power delivery network design beyond 5 nm","author":"Prasad","year":"2019","journal-title":"IEDM Tech. Dig."},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/isvlsi.2018.00022"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1016\/j.mejo.2022.105481","article-title":"ASAP5: A predictive PDK for the 5 nm node","volume":"126","author":"Vashishtha","year":"2022","journal-title":"Microelectron. J."},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/iitc.2018.8430489"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1117\/12.2258195"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/vlsit.2016.7573359"},{"key":"ref16","article-title":"Fabrication and characterization of gate-all-around stacked-nanowire\/nanosheet MOS transistors realized by a gate-last approach for sub-7 nm technology nodes","author":"Gaben","year":"2017"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2017.8268388"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1117\/12.2501680"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1117\/12.2584760"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265096"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/SBMicro.2014.6940082"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401055"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2016.7838497"},{"key":"ref24","first-page":"29","article-title":"Enabling sub-5 nm CMOS technology scaling thinner and taller!","author":"Ryckaert","year":"2019","journal-title":"IEDM Tech. Dig."},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/itc44170.2019.9000164"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265113"},{"key":"ref27","volume-title":"Synopsys","year":"2019"},{"key":"ref28","volume-title":"Predictive Technology Model","year":"2012"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnology18217.2020.9265025"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2018.2886446"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/devic.2019.8783300"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2018.2873008"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2017.2725325"},{"key":"ref34","volume-title":"Replacement metal gate and inner spacer formation in three dimensional structures using sacrificial silicon germanium","author":"Loubet","year":"2019"},{"key":"ref35","volume-title":"Sentaurus\u2122 Device User Guide","year":"2018"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1149\/1.2833317"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/iedm.2017.8268438"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2391632"},{"key":"ref39","volume-title":"Introducing 5 nm FinFET Technology in Microwind","year":"2021"},{"key":"ref40","volume-title":"BSIM-CMG Model","year":"2022"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3088392"},{"key":"ref42","first-page":"29","article-title":"A 10 nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects","author":"Auth","year":"2017","journal-title":"IEDM Tech. Dig."},{"key":"ref43","volume-title":"Historic Process Technologies Comparison","year":"2009"},{"key":"ref44","volume-title":"Introducing 7 nm FinFET technology in Microwind","year":"2017"},{"key":"ref45","volume-title":"TSMC 7nm HD and HP Cells, 2nd Gen 7 nm, and the Snapdragon 855 DTCO","year":"2019"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/vlsit.2004.1345476"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ICEmElec.2016.8074417"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2016.7573416"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223653"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2016.2554561"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2015.7223712"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1103\/physrevb.81.155454"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1103\/physrevb.79.041402"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1109\/IITC-AMC.2017.7968982"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/IITC.2018.8430407"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/iitc51362.2021.9537371"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/iitc51362.2021.9537559"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/IITC47697.2020.9515591"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1017\/S0305004100019952"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1080\/00018735200101151"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevB.1.1382"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3033510"},{"key":"ref63","first-page":"36","article-title":"Novel forksheet device architecture as ultimate logic scaling device towards 2 nm","author":"Weckx","year":"2019","journal-title":"IEDM Tech. Dig."},{"key":"ref64","volume-title":"OpenCores","year":"2021"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10019332\/09997505.pdf?arnumber=9997505","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T12:08:34Z","timestamp":1709381314000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9997505\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,2]]},"references-count":64,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2022.3229442","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,2]]}}}