{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,16]],"date-time":"2026-07-16T15:46:01Z","timestamp":1784216761028,"version":"3.55.0"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000161","name":"NIST","doi-asserted-by":"publisher","award":["60NANB20D20"],"award-info":[{"award-number":["60NANB20D20"]}],"id":[{"id":"10.13039\/100000161","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["SaTC-2020625"],"award-info":[{"award-number":["SaTC-2020625"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.1109\/tvlsi.2023.3242640","type":"journal-article","created":{"date-parts":[[2023,2,21]],"date-time":"2023-02-21T00:08:01Z","timestamp":1676938081000},"page":"596-600","source":"Crossref","is-referenced-by-count":6,"title":["COPMA: Compact and Optimized Polynomial Multiplier Accelerator for High-Performance Implementation of LWR-Based PQC"],"prefix":"10.1109","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3461-4548","authenticated-orcid":false,"given":"Pengzhou","family":"He","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Villanova University, Villanova, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1624-9500","authenticated-orcid":false,"given":"Yazheng","family":"Tu","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Villanova University, Villanova, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tianyou","family":"Bao","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Villanova University, Villanova, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8066-221X","authenticated-orcid":false,"given":"Leonel","family":"Sousa","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering Department (DEEC), Instituto Superior Técnico (IST), Universidade de Lisboa, Lisbon, Portugal"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4814-1318","authenticated-orcid":false,"given":"Jiafeng","family":"Xie","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Villanova University, Villanova, PA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/SFCS.1994.365700"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VTS48691.2020.9107585"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-88702-7_5"},{"key":"ref4","volume-title":"PQC Round 3 Submissions"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1568318.1568324"},{"key":"ref6","first-page":"1","volume-title":"SABER: Mod-LWR Based KEM (Round 3 Submission)","author":"D\u2019Anvers","year":"2021"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.6028\/nist.ir.8413"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.46586\/tches.v2020.i4.443-466"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3048395"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218727"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586219"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS48785.2022.9937496"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2022.3160394"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00032"},{"key":"ref15","article-title":"Low-latency VLSI architectures for modular polynomial multiplication via fast filtering and applications to lattice-based cryptography","author":"Tan","year":"2021","journal-title":"arXiv:2110.12127"},{"key":"ref16","first-page":"1","article-title":"A unified cryptoprocessor for lattice-based signature and key-exchange","author":"Mert","journal-title":"IEEE Trans. Comput."},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2922999"},{"key":"ref18","first-page":"1","article-title":"Filianore: Better multiplier architectures for LWE-based post-quantum key exchange","volume-title":"Proc. 56th Annu. Design Autom. Conf.","author":"Bian"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3188943"},{"key":"ref20","first-page":"1","article-title":"NIST post-quantum cryptography\u2014A hardware evaluation study","author":"Basu","year":"2019","journal-title":"Cryptol. ePrint Arch."}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/10079225\/10048766-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10079225\/10048766.pdf?arnumber=10048766","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,13]],"date-time":"2024-02-13T18:04:47Z","timestamp":1707847487000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10048766\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":20,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2023.3242640","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,4]]}}}