{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T16:40:46Z","timestamp":1781887246025,"version":"3.54.5"},"reference-count":43,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2023,5,1]],"date-time":"2023-05-01T00:00:00Z","timestamp":1682899200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,5,1]],"date-time":"2023-05-01T00:00:00Z","timestamp":1682899200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,5,1]],"date-time":"2023-05-01T00:00:00Z","timestamp":1682899200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100002418","name":"Strategic CAD Labs, Intel Corporation, USA","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2023,5]]},"DOI":"10.1109\/tvlsi.2023.3250662","type":"journal-article","created":{"date-parts":[[2023,3,16]],"date-time":"2023-03-16T18:04:58Z","timestamp":1678989898000},"page":"670-683","source":"Crossref","is-referenced-by-count":10,"title":["Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers"],"prefix":"10.1109","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9294-1603","authenticated-orcid":false,"given":"Sumit K.","family":"Mandal","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin&#x2014;Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shruti Yadav","family":"Narayana","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin&#x2014;Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1175-2983","authenticated-orcid":false,"given":"Raid","family":"Ayoub","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael","family":"Kishinevsky","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ahmed","family":"Abousamra","sequence":"additional","affiliation":[{"name":"Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5045-5535","authenticated-orcid":false,"given":"Umit Y.","family":"Ogras","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin&#x2014;Madison, Madison, WI, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2017.38"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3416850"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2004.1330747"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.78"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2016.25"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2020.3015509"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2022.3169899"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9473949"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC52403.2022.9712530"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3358176"},{"key":"ref12","first-page":"1","article-title":"Performance analysis of priority-aware NoCs with deflection routing under traffic congestion","volume-title":"Proc. 39th Int. Conf. Comput.-Aided Design","author":"Mandal"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/2897937.2898075"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2010691"},{"key":"ref16","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally","year":"2004"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01755-1"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/581199.581253"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/AICCSA.2009.5069347"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CESA.2006.4281893"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2012.93"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2020.3013003"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2178620"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2061613"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2474393"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/j.comcom.2010.07.007"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643448"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1007\/BF02023095"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1016\/0166-5316(87)90057-5"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/12.135558"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/NoCS.2013.6558403"},{"key":"ref32","volume-title":"Analysis and optimization of discrete-time generalized processor sharing queues","author":"Vanlerberghe","year":"2018"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2010.5647577"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2016.2556007"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/BFb0013856"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1002\/0471791571"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2006.878263"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/3139540.3139541"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3185768.3185771"},{"key":"ref40","first-page":"72","article-title":"The PARSEC benchmark suite: Characterization and architectural implications","volume-title":"Proc. 17th Int. Conf. Parallel Archit. Compilation Techn.","author":"Bienia"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1145\/2347655.2347669"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"},{"key":"ref43","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-45318-0","volume-title":"Network Calculus: A Theory of Deterministic Queuing Systems for the Internet","author":"Boudec","year":"2001"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10106533\/10072009.pdf?arnumber=10072009","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,3]],"date-time":"2024-03-03T06:38:57Z","timestamp":1709447937000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10072009\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,5]]},"references-count":43,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2023.3250662","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,5]]}}}