{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T23:40:49Z","timestamp":1783035649600,"version":"3.54.6"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2023,10]]},"DOI":"10.1109\/tvlsi.2023.3299509","type":"journal-article","created":{"date-parts":[[2023,8,8]],"date-time":"2023-08-08T17:49:05Z","timestamp":1691516945000},"page":"1592-1602","source":"Crossref","is-referenced-by-count":29,"title":["H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention"],"prefix":"10.1109","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8288-393X","authenticated-orcid":false,"given":"Wantong","family":"Li","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Madison","family":"Manley","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0753-6257","authenticated-orcid":false,"given":"James","family":"Read","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0301-1349","authenticated-orcid":false,"given":"Ankit","family":"Kaul","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Muhannad S.","family":"Bakir","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0068-3652","authenticated-orcid":false,"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830211"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2010.2041893"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062979"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3223966"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731754"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774692"},{"key":"ref14","first-page":"252","article-title":"An 89 TOPS\/W and 16.3 TOPS\/mm2 all-digital SRAM-based full-precision compute-in memory macro in 22 nm for machine-learning edge applications","author":"chih","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2022.3223031"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS51828.2021.9458501"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993491"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510676"},{"key":"ref33","doi-asserted-by":"crossref","first-page":"181","DOI":"10.1109\/TCPMT.2010.2101890","article-title":"High-frequency scalable electrical model and analysis of a through silicon via (TSV)","volume":"1","author":"kim","year":"2011","journal-title":"IEEE Trans Compon Packag Manuf Technol"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662395"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS57966.2023.10168651"},{"key":"ref2","article-title":"An image is worth 16?16 words: Transformers for image recognition at scale","author":"dosovitskiy","year":"2020","journal-title":"arXiv 2010 11929"},{"key":"ref1","first-page":"1","article-title":"Attention is all you need","author":"vaswani","year":"2017","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2022.3182935"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474146"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830438"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00018"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32862.2020.00099"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC53440.2021.9631765"},{"key":"ref24","first-page":"478","article-title":"An N40 256K?44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance","author":"chou","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2021.3092436"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2021.3050715"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3231570"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3163197"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3141370"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3252486"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s11263-015-0816-y"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-022-00795-x"},{"key":"ref41","first-page":"466","article-title":"A 28 nm 15.59 ?J\/token full-digital bitline-transpose CIM-based sparse transformer accelerator with pipeline\/parallel reconfigurable modes","volume":"65","author":"tu","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137196"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3111857"},{"key":"ref21","first-page":"740","article-title":"Microsoft COCO: Common objects in context","author":"lin","year":"2014","journal-title":"Proc Eur Conf Comput Vis (ECCV)"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3042411"},{"key":"ref28","first-page":"1","article-title":"Advanced packaging: Enabling Moore’s law’s next frontier through heterogeneous integration","author":"swaminathan","year":"2021","journal-title":"Proc IEEE Hot Chip Conf"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2958568"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3233396"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-020-0655-z"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3508396.3512869"},{"key":"ref9","first-page":"496","article-title":"A 65 nm 4 Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS\/W fully parallel product-sum operation for binary DNN edge processors","author":"khwa","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","first-page":"9355","article-title":"Twins: Revisiting the design of spatial attention in vision transformers","author":"chu","year":"2021","journal-title":"Proc Adv Neural Inf Process Syst"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV48922.2021.00061"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV48922.2021.00986"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415640"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10261320\/10213232.pdf?arnumber=10213232","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,9]],"date-time":"2023-10-09T19:46:04Z","timestamp":1696880764000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10213232\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10]]},"references-count":47,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2023.3299509","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,10]]}}}