{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,4]],"date-time":"2026-02-04T17:42:52Z","timestamp":1770226972485,"version":"3.49.0"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2022YFB4401900"],"award-info":[{"award-number":["2022YFB4401900"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62004052"],"award-info":[{"award-number":["62004052"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62174047"],"award-info":[{"award-number":["62174047"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62022065"],"award-info":[{"award-number":["62022065"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["U19A2053"],"award-info":[{"award-number":["U19A2053"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62090040"],"award-info":[{"award-number":["62090040"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004731","name":"Zhejiang Provincial Natural Science Foundation of China","doi-asserted-by":"publisher","award":["LQ21F040002"],"award-info":[{"award-number":["LQ21F040002"]}],"id":[{"id":"10.13039\/501100004731","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2023,11]]},"DOI":"10.1109\/tvlsi.2023.3302842","type":"journal-article","created":{"date-parts":[[2023,8,15]],"date-time":"2023-08-15T17:36:00Z","timestamp":1692120960000},"page":"1870-1873","source":"Crossref","is-referenced-by-count":3,"title":["An 8-bit 1.5-GS\/s Two-Step SAR ADC With Embedded Interstage Gain"],"prefix":"10.1109","volume":"31","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2586-3772","authenticated-orcid":false,"given":"Yi","family":"Shen","sequence":"first","affiliation":[{"name":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Junyan","family":"Hao","sequence":"additional","affiliation":[{"name":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9942-0069","authenticated-orcid":false,"given":"Shubin","family":"Liu","sequence":"additional","affiliation":[{"name":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zeshuai","family":"An","sequence":"additional","affiliation":[{"name":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9913-4644","authenticated-orcid":false,"given":"Dengquan","family":"Li","sequence":"additional","affiliation":[{"name":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9296-535X","authenticated-orcid":false,"given":"Ruixue","family":"Ding","sequence":"additional","affiliation":[{"name":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7764-1928","authenticated-orcid":false,"given":"Zhangming","family":"Zhu","sequence":"additional","affiliation":[{"name":"Key Laboratory of Analog Integrated Circuits and Systems (Ministry of Education), School of Microelectronics, Xidian University, Xi&#x2019;an, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","first-page":"1","article-title":"An 8b 1.0-to-1.25 GS\/s 0.7-to-0.8V single-stage time-based gated-ring-oscillator ADC with 2? interpolating sense-amplifier-latches","author":"yonar","year":"2023","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662290"},{"key":"ref14","first-page":"16","article-title":"A 7b 4.5 GS\/s 4? interleaved SAR ADC with fully on-chip background timing skew calibration","author":"wang","year":"2023","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3169508"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2876874"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3166792"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502370"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682839"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2732731"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2785349"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2384025"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10287007\/10220116.pdf?arnumber=10220116","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,6]],"date-time":"2023-11-06T20:04:37Z","timestamp":1699301077000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10220116\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11]]},"references-count":14,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2023.3302842","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,11]]}}}