{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T18:17:05Z","timestamp":1763749025198,"version":"3.37.3"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,2,1]],"date-time":"2024-02-01T00:00:00Z","timestamp":1706745600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program","doi-asserted-by":"publisher","award":["2018YFB2202900"],"award-info":[{"award-number":["2018YFB2202900"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"publisher","award":["92364202","61934005"],"award-info":[{"award-number":["92364202","61934005"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2024,2]]},"DOI":"10.1109\/tvlsi.2023.3318744","type":"journal-article","created":{"date-parts":[[2023,10,10]],"date-time":"2023-10-10T19:42:20Z","timestamp":1696966940000},"page":"283-290","source":"Crossref","is-referenced-by-count":2,"title":["Write\u2013Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-4893-7907","authenticated-orcid":false,"given":"Junjie","family":"An","sequence":"first","affiliation":[{"name":"School of Microelectronics, University of Science and Technology of China, Hefei, China"}]},{"given":"Zhidao","family":"Zhou","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3740-9868","authenticated-orcid":false,"given":"Linfang","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7636-0227","authenticated-orcid":false,"given":"Wang","family":"Ye","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"given":"Weizeng","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"given":"Hanghang","family":"Gao","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"given":"Zhi","family":"Li","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"given":"Jinghui","family":"Tian","sequence":"additional","affiliation":[{"name":"Frontier Institute of Chip and System, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1259-6310","authenticated-orcid":false,"given":"Yan","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2291-9598","authenticated-orcid":false,"given":"Hongyang","family":"Hu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8234-7400","authenticated-orcid":false,"given":"Jinshan","family":"Yue","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1400-4040","authenticated-orcid":false,"given":"Lingyan","family":"Fan","sequence":"additional","affiliation":[{"name":"Department of Communication Engineering, Hangzhou Dianzi University, Hangzhou, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6220-4461","authenticated-orcid":false,"given":"Shibing","family":"Long","sequence":"additional","affiliation":[{"name":"School of Microelectronics, University of Science and Technology of China, Hefei, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7062-831X","authenticated-orcid":false,"given":"Qi","family":"Liu","sequence":"additional","affiliation":[{"name":"Frontier Institute of Chip and System, State Key Laboratory of ASIC and System, Fudan University, Shanghai, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2192-9655","authenticated-orcid":false,"given":"Chunmeng","family":"Dou","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nature14539"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0059-3"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586232"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC56115.2022.9980744"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s10832-017-0095-9"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510627"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0117-x"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2018.2890229"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-019-0288-0"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.2976115"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-00505-5"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-0435-7"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720557"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720546"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-021-00676-9"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-022-00795-x"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746281"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177079"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2013.6487708"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757457"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310392"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2019.8776570"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993514"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662393"},{"key":"ref25","first-page":"1","article-title":"A 14 nm 100Kb 2T1R transpose RRAM with >150X resistance ratio enhancement and 27.95% reduction on energy-latency product using low-power near threshold read operation and fast data-line current stabling scheme","volume-title":"Proc. Symp. VLSI Technol.","author":"Wang"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365945"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662402"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3045369"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3140753"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2018.2879788"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3010795"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3015940"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3141370"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3163197"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510676"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10411971\/10275806.pdf?arnumber=10275806","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,3]],"date-time":"2024-06-03T17:54:09Z","timestamp":1717437249000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10275806\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,2]]},"references-count":35,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2023.3318744","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2024,2]]}}}