{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,31]],"date-time":"2025-12-31T12:04:14Z","timestamp":1767182654143,"version":"3.37.3"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100004735","name":"Hunan Natural Science Foundation","doi-asserted-by":"publisher","award":["2023JJ30637"],"award-info":[{"award-number":["2023JJ30637"]}],"id":[{"id":"10.13039\/501100004735","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100019081","name":"Science and Technology Innovation Program of Hunan Province","doi-asserted-by":"publisher","award":["2023RC3014"],"award-info":[{"award-number":["2023RC3014"]}],"id":[{"id":"10.13039\/501100019081","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Scientific Research Project","award":["ZD0102088845"],"award-info":[{"award-number":["ZD0102088845"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62034005","61704192"],"award-info":[{"award-number":["62034005","61704192"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2024,1]]},"DOI":"10.1109\/tvlsi.2023.3328592","type":"journal-article","created":{"date-parts":[[2023,11,7]],"date-time":"2023-11-07T19:33:27Z","timestamp":1699385607000},"page":"137-149","source":"Crossref","is-referenced-by-count":5,"title":["CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-8239-467X","authenticated-orcid":false,"given":"Pengcheng","family":"Huang","sequence":"first","affiliation":[{"name":"Key Laboratory of Advanced Microprocessor Chips and Systems, Microelectronics and Microprocessor Institute, School of Computer, National University of Defense Technology, Changsha, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9556-5535","authenticated-orcid":false,"given":"Yaohua","family":"Wang","sequence":"additional","affiliation":[{"name":"Key Laboratory of Advanced Microprocessor Chips and Systems, Microelectronics and Microprocessor Institute, School of Computer, National University of Defense Technology, Changsha, China"}]},{"given":"Zhenyu","family":"Zhao","sequence":"additional","affiliation":[{"name":"Key Laboratory of Advanced Microprocessor Chips and Systems, Microelectronics and Microprocessor Institute, School of Computer, National University of Defense Technology, Changsha, China"}]},{"given":"Daheng","family":"Yue","sequence":"additional","affiliation":[{"name":"Key Laboratory of Advanced Microprocessor Chips and Systems, Microelectronics and Microprocessor Institute, School of Computer, National University of Defense Technology, Changsha, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/3505170.3511476"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2889756"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/2872334.2872349"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2949514"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID2022.2022.00027"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000729"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIDCS47293.2020.9179954"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775989"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488846"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147171"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.673631"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.825875"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2394310"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062184"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2007.373394"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2011.2106852"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160943"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514965"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159695"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2834437"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966750"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.41"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2169308"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2001.912617"},{"volume-title":"Power Analysis of Clock Gating at RTL","year":"2010","author":"Koduri","key":"ref25"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2018.8297374"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2190535"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3122109"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878292"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2902215"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/2160916.2160950"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/4.918917"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593171"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2560524"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10375851\/10311538.pdf?arnumber=10311538","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,4,3]],"date-time":"2024-04-03T18:02:31Z","timestamp":1712167351000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10311538\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1]]},"references-count":34,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2023.3328592","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2024,1]]}}}