{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,13]],"date-time":"2026-03-13T14:55:21Z","timestamp":1773413721086,"version":"3.50.1"},"reference-count":45,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,4,1]],"date-time":"2024-04-01T00:00:00Z","timestamp":1711929600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["IIS\/CPS-1652038"],"award-info":[{"award-number":["IIS\/CPS-1652038"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2024,4]]},"DOI":"10.1109\/tvlsi.2024.3355499","type":"journal-article","created":{"date-parts":[[2024,2,2]],"date-time":"2024-02-02T18:45:37Z","timestamp":1706899537000},"page":"633-644","source":"Crossref","is-referenced-by-count":9,"title":["FSpGEMM: A Framework for Accelerating Sparse General Matrix\u2013Matrix Multiplication Using Gustavson\u2019s Algorithm on FPGAs"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3248-9301","authenticated-orcid":false,"given":"Erfan","family":"Bank Tavakoli","sequence":"first","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]},{"given":"Michael","family":"Riera","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6939-1669","authenticated-orcid":false,"given":"Masudul Hassan","family":"Quraishi","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6509-8753","authenticated-orcid":false,"given":"Fengbo","family":"Ren","sequence":"additional","affiliation":[{"name":"Arizona State University, Tempe, AZ, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1137\/1.9780898719505","volume-title":"A Multigrid Tutorial","author":"Briggs","year":"2000"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/0196-6774(89)90005-9"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080254"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/9781119079231"},{"key":"ref5","first-page":"1","article-title":"Are FPGAs suitable for edge computing?","volume-title":"Proc. USENIX Workshop Hot Topics Edge Comput.","author":"Biookaghazadeh"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1002\/cta.796"},{"issue":"3","key":"ref7","first-page":"667","article-title":"The algorithms for FPGA implementation of sparse matrices multiplication","volume":"33","author":"Jamro","year":"2014","journal-title":"Comput. Informat."},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM48280.2020.00028"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3281719"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00068"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2049662.2049663"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00067"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00030"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960480"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3445814.3446702"},{"key":"ref16","article-title":"Cusparse library","volume-title":"Proc. GPU Technol. Conf.","author":"Naumov"},{"key":"ref17","volume-title":"CUSP: Generic Parallel Algorithms for Sparse Matrix and Graph Computations, Version 0.5.0","author":"Dalton","year":"2014"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.2017.19"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1137\/130948811"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3293883.3295701"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2014.47"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3332466.3374521"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/3503221.3508431"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2930057"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICPR.2018.8545462"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2017.7995254"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3582016.3582047"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3458744.3473352"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3332466.3374546"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/3293883.3295712"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1145\/331532.331562"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1007\/s11265-022-01821-z"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2011.05.005"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1137\/S0895479894278952"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.2008.96"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-8675-3_14"},{"key":"ref37","first-page":"7\u20131","volume-title":"A software package for partitioning unstructured graphs, partitioning meshes, and computing fill-reducing orderings of sparse matrices","author":"Karypis","year":"1998"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/1583991.1584053"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3208040.3208062"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2008.4536313"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2014.125"},{"key":"ref42","first-page":"75","article-title":"Accelerating the LOBPCG method on GPUs using a blocked sparse matrix vector product","volume-title":"Proc. SpringSim (HPS)","author":"Anzt"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.208"},{"key":"ref44","volume-title":"Intel FPGA SDK for Opencl Pro Edition: Programming Guide","year":"2022"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10136958"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/10477564\/10419187-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10477564\/10419187.pdf?arnumber=10419187","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,26]],"date-time":"2024-03-26T21:18:00Z","timestamp":1711487880000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10419187\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,4]]},"references-count":45,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3355499","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,4]]}}}