{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,25]],"date-time":"2026-02-25T09:14:25Z","timestamp":1772010865071,"version":"3.50.1"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Thales Research and Technology Canada, Prompt Innov, and Canada's Natural Sciences and Engineering Research Council","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2024,6]]},"DOI":"10.1109\/tvlsi.2024.3360370","type":"journal-article","created":{"date-parts":[[2024,3,22]],"date-time":"2024-03-22T18:14:04Z","timestamp":1711131244000},"page":"1124-1135","source":"Crossref","is-referenced-by-count":3,"title":["Analyzing the Vulnerabilities of External SDRAM on System-on-Chip Field Programmable Gate Array Devices"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7075-9632","authenticated-orcid":false,"given":"Alexandre","family":"Proulx","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Laval University, Qu&#x00E9;bec City, QC, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7904-6137","authenticated-orcid":false,"given":"Jean-Yves","family":"Chouinard","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Laval University, Qu&#x00E9;bec City, QC, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1766-7528","authenticated-orcid":false,"given":"Amine","family":"Miled","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Laval University, Qu&#x00E9;bec City, QC, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7368-9484","authenticated-orcid":false,"given":"Paul","family":"Fortier","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Laval University, Qu&#x00E9;bec City, QC, Canada"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"XQ Defense\u2014Grade Portfolio Product Selection Guide","year":"2021"},{"key":"ref2","volume-title":"UG585 Zynq-7000 SoC Technical Reference Manual V1.12.2","year":"2019"},{"key":"ref3","volume-title":"MNL1100\u2014Intel Agilex Hard Processor System Technical Reference Manual (v21.3)","year":"2021"},{"key":"ref4","volume-title":"S105v4\u2014Intel Stratix 10 Hard Processor System Technical Reference Manual (v21.3)","year":"2021"},{"key":"ref5","article-title":"Row hammer refresh command","author":"Bains","year":"2014"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853210"},{"key":"ref7","volume-title":"Exploiting the DRAM Rowhammer Bug to Gain Kernel Privileges","author":"Seaborn","year":"2015"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-40667-1_15"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-66787-4_21"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/sp40000.2020.00020"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1506409.1506429"},{"key":"ref12","first-page":"1","article-title":"Taking DMA attacks to the next level: How to do arbitrary reads\/writes in a live and unmodified system using a rogue memory controller","volume-title":"Proc. Blackhat USA","author":"Trikalinou"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2000.894234"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2879878"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE51398.2021.9474026"},{"key":"ref16","first-page":"487","article-title":"An off-chip attack on hardware enclaves via the memory bus","volume-title":"Proc. 29th USENIX Conf. Secur. Symp.","author":"Lee"},{"key":"ref17","volume-title":"JESD79-3E\u2014DDR3 SDRAM Specification","year":"2010"},{"key":"ref18","volume-title":"How to Do PCB Trace Length Matching vs. Frequency","author":"Peterson","year":"2021"},{"key":"ref19","volume-title":"All About Your PCB Trace Length: How Long is Too Long?","author":"Peterson","year":"2021"},{"key":"ref20","first-page":"7","article-title":"Insertion loss comparisons of common high frequency PCB constructions","volume-title":"Proc. IPC APEX Expo","author":"Coonrod"},{"key":"ref21","volume-title":"UG933\u2014Zynq-7000 SoC PCB Design Guide (v1.13.1)","year":"2019"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2020.3005484"},{"key":"ref23","volume-title":"W2637A, W2638A and W2639A LPDDR BGA Probes for Logic Analyzers and Oscilloscopes\u2014Data Sheet","year":"2014"},{"key":"ref24","volume-title":"AN1\u2014Probing Tips for High Performance Design and Measurement","year":"2022"},{"key":"ref25","volume-title":"U-Boot-XLNX","year":"2016"},{"key":"ref26","volume-title":"UG586\u2014Zynq-7000 SoC and 7 Series Devices Memory Interface Solutions (v4.2)","year":"2018"},{"key":"ref27","volume-title":"Lightweight AXI-4 DDR3 Controller","author":"Embedded","year":"2020"},{"key":"ref28","volume-title":"Application of Attack Potential to Smartcards and Similar Devices Version 3.0","year":"2020"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3287624.3288742"},{"key":"ref30","volume-title":"DS890\u2014UltraScale Architecture and Product Data Sheet: Overview (v4.0)","year":"2021"},{"key":"ref31","volume-title":"DS950\u2014Versal Architecture and Product Data Sheet: Overview (v1.14)","year":"2021"},{"key":"ref32","volume-title":"AGOverview\u2014Intel \u00ae AgilexT FPGAs and SoCs Device Overview","year":"2021"},{"key":"ref33","volume-title":"S10TXOVERVIEW\u2014Intel \u00ae Stratix \u00aeTX Device Overview","year":"2020"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ACSAC.2006.21"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2006.22"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.16"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.23919\/FPL.2017.8056797"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2487726.2488368"},{"key":"ref39","first-page":"12","author":"Kaplan","year":"2021","journal-title":"AMD Memory Encryption"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10536717\/10478320.pdf?arnumber=10478320","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T04:38:55Z","timestamp":1725338335000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10478320\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6]]},"references-count":39,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3360370","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,6]]}}}