{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,19]],"date-time":"2026-05-19T15:03:51Z","timestamp":1779203031355,"version":"3.51.4"},"reference-count":46,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T00:00:00Z","timestamp":1719792000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T00:00:00Z","timestamp":1719792000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,7,1]],"date-time":"2024-07-01T00:00:00Z","timestamp":1719792000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100010418","name":"Institute for Information Communications Technology Promotion","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100010418","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Korea Government Ministry of Science, Information and Communication Technology and Future Planning (MSIP)","award":["2021-0-00754"],"award-info":[{"award-number":["2021-0-00754"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2024,7]]},"DOI":"10.1109\/tvlsi.2024.3378197","type":"journal-article","created":{"date-parts":[[2024,5,6]],"date-time":"2024-05-06T18:18:34Z","timestamp":1715019514000},"page":"1205-1215","source":"Crossref","is-referenced-by-count":8,"title":["Factored Systolic Arrays Based on Radix-8 Multiplication for Machine Learning Acceleration"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5504-6274","authenticated-orcid":false,"given":"Kashif","family":"Inayat","sequence":"first","affiliation":[{"name":"Barcelona Supercomputing Center, Barcelona, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2457-7309","authenticated-orcid":false,"given":"Inayat","family":"Ullah","sequence":"additional","affiliation":[{"name":"ARM, Trondheim, Norway"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5819-1995","authenticated-orcid":false,"given":"Jaeyong","family":"Chung","sequence":"additional","affiliation":[{"name":"Department of System Semiconductor Engineering, Yonsei University, Seoul, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1201\/9781482283198"},{"key":"ref2","first-page":"1097","article-title":"ImageNet classification with deep convolutional neural networks","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Krizhevsky"},{"key":"ref3","first-page":"2922","article-title":"Real-time adaptive image compression","volume-title":"Proc. 34th Int. Conf. Mach. Learn.","author":"Rippel"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MCI.2018.2840738"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1038\/nature24270"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.2200\/s00677ed1v01y201511cac034"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2017.2761740"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.2200\/s01004ed1v01y202004cac050"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-04666-8_21"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.30"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.435"},{"key":"ref14","first-page":"815","article-title":"MEC: Memory-efficient convolution for deep neural network","volume-title":"Proc. Int. Conf. Mach. Learn.","author":"Cho"},{"key":"ref15","volume-title":"Algorithms for VLSI Processor Arrays","author":"Kung","year":"1979"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1982.1653825"},{"key":"ref17","first-page":"1737","article-title":"Deep learning with limited numerical precision","volume-title":"Proc. Int. Conf. Mach. Learn.","author":"Gupta"},{"key":"ref18","volume-title":"System Architecture","year":"2019"},{"key":"ref19","volume-title":"Accelerating DNNs With Xilinx Alveo Accelerator Cards","year":"2018"},{"key":"ref20","volume-title":"NVIDIA Deep Learning Accelerator(NVDLA)","year":"2018"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/EMC249363.2019.00012"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ICPADS.2017.00034"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/SiPS.2018.8598454"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2019.8702753"},{"key":"ref25","article-title":"SCALE-sim: Systolic CNN accelerator simulator","author":"Samajdar","year":"2018","journal-title":"arXiv:1811.02883"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218585"},{"key":"ref27","article-title":"Gemmini: Enabling systematic deep-learning architecture evaluation via full-stack integration","author":"Genc","year":"2019","journal-title":"arXiv:1911.09925"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2020.2979965"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2866172"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927163"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/82.618039"},{"key":"ref32","article-title":"Fast multiplication algorithms and implementation","author":"Bewick","year":"1994"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/SECON.2002.995633"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.2003.1207665"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.1999.831921"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2000.862391"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2017.2656880"},{"key":"ref38","first-page":"229","article-title":"A multiple-precision multiply and accumulation design with multiply-add merged strategy for AI accelerating","volume-title":"Proc. 26th Asia South Pacific Design Autom. Conf.","author":"Zhang"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2018.2873716"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.3390\/electronics10060652"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3170233"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/3597031.3597056"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.3390\/s23094297"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1093\/qjmam\/4.2.236"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1016\/b978-1-55860-798-9.x5000-3"},{"key":"ref46","volume-title":"Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine","author":"Sawada","year":"2022"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/92\/10576042\/10520269.pdf?arnumber=10520269","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,6,29]],"date-time":"2024-06-29T05:13:05Z","timestamp":1719637985000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10520269\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7]]},"references-count":46,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3378197","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,7]]}}}