{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T15:54:01Z","timestamp":1779378841556,"version":"3.53.1"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2024,11,1]],"date-time":"2024-11-01T00:00:00Z","timestamp":1730419200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,11,1]],"date-time":"2024-11-01T00:00:00Z","timestamp":1730419200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,11,1]],"date-time":"2024-11-01T00:00:00Z","timestamp":1730419200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001381","name":"National Research Foundation, Singapore under its CRP","doi-asserted-by":"publisher","award":["NRF-CRP23-2019-0003"],"award-info":[{"award-number":["NRF-CRP23-2019-0003"]}],"id":[{"id":"10.13039\/501100001381","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100010002","name":"Ministry of Education, Singapore under its Academic Research Fund Tier-2","doi-asserted-by":"publisher","award":["MOE-T2EP50122-0024"],"award-info":[{"award-number":["MOE-T2EP50122-0024"]}],"id":[{"id":"10.13039\/100010002","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2024,11]]},"DOI":"10.1109\/tvlsi.2024.3409652","type":"journal-article","created":{"date-parts":[[2024,6,24]],"date-time":"2024-06-24T20:16:51Z","timestamp":1719260211000},"page":"2085-2092","source":"Crossref","is-referenced-by-count":3,"title":["1.63 pJ\/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9836-3023","authenticated-orcid":false,"given":"Dongrui","family":"Li","sequence":"first","affiliation":[{"name":"Singapore University of Technology and Design, Tampines, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ming Ming","family":"Wong","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Fusionopolis, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yi Sheng","family":"Chong","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Fusionopolis, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jun","family":"Zhou","sequence":"additional","affiliation":[{"name":"Institute of High Performance Computing, Agency for Science, Technology and Research (A*STAR), Fusionopolis, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohit","family":"Upadhyay","sequence":"additional","affiliation":[{"name":"Department of Computer Science, National University of Singapore, Queenstown, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ananta","family":"Balaji","sequence":"additional","affiliation":[{"name":"Department of Computer Science, National University of Singapore, Queenstown, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Aarthy","family":"Mani","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Fusionopolis, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4281-2053","authenticated-orcid":false,"given":"Weng Fai","family":"Wong","sequence":"additional","affiliation":[{"name":"Department of Computer Science, National University of Singapore, Queenstown, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9010-6519","authenticated-orcid":false,"given":"Li Shiuan","family":"Peh","sequence":"additional","affiliation":[{"name":"Department of Computer Science, National University of Singapore, Queenstown, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8320-6818","authenticated-orcid":false,"given":"Anh Tuan","family":"Do","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Fusionopolis, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9199-0799","authenticated-orcid":false,"given":"Bo","family":"Wang","sequence":"additional","affiliation":[{"name":"Singapore University of Technology and Design, Tampines, Singapore"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1142\/S0129065709002002"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.3389\/fnsyn.2012.00002"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1978542.1978559"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2970709"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3279349"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3013810"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/a-sscc48613.2020.9336142"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3112979"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/essderc53440.2021.9631786"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662398"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365943"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731734"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/vlsic.2018.8502423"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2889670"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116516"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TBCAS.2017.2759700"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10736447\/10570234.pdf?arnumber=10570234","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,27]],"date-time":"2024-11-27T00:28:18Z","timestamp":1732667298000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10570234\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,11]]},"references-count":16,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3409652","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,11]]}}}