{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,29]],"date-time":"2025-10-29T06:28:29Z","timestamp":1761719309035,"version":"3.37.3"},"reference-count":20,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"CHIMES, one of Semiconductor Research Corporation (SRC)\/Defense Advanced Research Projects Agency (DARPA) Joint University Microelectronics Program (JUMP) 2.0 Center."}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2024,9]]},"DOI":"10.1109\/tvlsi.2024.3415481","type":"journal-article","created":{"date-parts":[[2024,6,28]],"date-time":"2024-06-28T18:20:27Z","timestamp":1719598827000},"page":"1718-1725","source":"Crossref","is-referenced-by-count":1,"title":["Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads"],"prefix":"10.1109","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5793-075X","authenticated-orcid":false,"given":"Yuan-Chun","family":"Luo","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4415-0866","authenticated-orcid":false,"given":"Anni","family":"Lu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1438-2439","authenticated-orcid":false,"given":"Janak","family":"Sharda","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Moritz","family":"Scherer","sequence":"additional","affiliation":[{"name":"Meta Reality Lab Research, Menlo Park, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7918-4655","authenticated-orcid":false,"given":"Jorge","family":"Tomas Gomez","sequence":"additional","affiliation":[{"name":"Meta Reality Lab Research, Menlo Park, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0086-1076","authenticated-orcid":false,"given":"Syed","family":"Shakib Sarwar","sequence":"additional","affiliation":[{"name":"Meta Reality Lab Research, Menlo Park, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6070-6310","authenticated-orcid":false,"given":"Ziyun","family":"Li","sequence":"additional","affiliation":[{"name":"Meta Reality Lab Research, Menlo Park, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Reid","family":"Frederick Pinkham","sequence":"additional","affiliation":[{"name":"Meta Reality Lab Research, Menlo Park, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0810-9903","authenticated-orcid":false,"given":"Barbara","family":"De Salvo","sequence":"additional","affiliation":[{"name":"Meta Reality Lab Research, Menlo Park, CA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0068-3652","authenticated-orcid":false,"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2016.2616357"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/mcas.2021.3092533"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/iedm19573.2019.8993491"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2017.2654506"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310392"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/iedm.2017.8268425"},{"key":"ref8","first-page":"11","article-title":"A 28 nm HKMG super low power embedded NVM technology based on ferroelectric FETs","volume-title":"IEDM Tech. Dig.","author":"Trentzsch"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM45625.2022.10019499"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/eptc56328.2022.10013108"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3386569.3392452"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00474"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2022.3170152"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3214170"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2021.3111857"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2014.2364742"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS51828.2021.9458501"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.12"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/3460233"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2013.6557149"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10648891\/10576629.pdf?arnumber=10576629","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,31]],"date-time":"2024-08-31T04:44:26Z","timestamp":1725079466000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10576629\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9]]},"references-count":20,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3415481","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2024,9]]}}}