{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T10:53:52Z","timestamp":1780397632551,"version":"3.54.1"},"reference-count":39,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100003052","name":"Ministry of Trade, Industry and Energy","doi-asserted-by":"publisher","award":["20019363"],"award-info":[{"award-number":["20019363"]}],"id":[{"id":"10.13039\/501100003052","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Korea Semiconductor Research Consortium (KSRC) Support Program for the Development of the Future Semiconductor Device"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,2]]},"DOI":"10.1109\/tvlsi.2024.3454286","type":"journal-article","created":{"date-parts":[[2024,9,13]],"date-time":"2024-09-13T19:18:34Z","timestamp":1726255114000},"page":"462-474","source":"Crossref","is-referenced-by-count":2,"title":["Effective Parallel Redundancy Analysis Using GPU for Memory Repair"],"prefix":"10.1109","volume":"33","author":[{"given":"Seung Ho","family":"Shin","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Computer Systems Reliable SoC Laboratory, Yonsei University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6868-0829","authenticated-orcid":false,"given":"Hayoung","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Intelligence Semiconductor Engineering, Ajou University, Suwon-si, Gyeonggi-do, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7093-2095","authenticated-orcid":false,"given":"Sungho","family":"Kang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Computer Systems Reliable SoC Laboratory, Yonsei University, Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805645"},{"key":"ref2","volume-title":"Fault Tolerance and Reliability Techniques for High Density Random Access Memories","author":"Chakraborty","year":"2002"},{"key":"ref3","volume-title":"High Performance Memory Testing: Design Principle, Fault Modeling and Self-Test","author":"Adams","year":"2003"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2002.1011170"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1977.1674761"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675739"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.55188"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2006.20"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1981.1051630"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1985.294737"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.1987.295111"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2044846"},{"key":"ref13","first-page":"175","article-title":"Defect analysis system speeds test and repair of redundant memories","volume":"57","author":"Tarr","year":"1984","journal-title":"Electronics"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1986.1586118"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TR.2006.874942"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.11.0211.0378"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.4218\/etrij.13.0112.0467"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2760505"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2954549"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3370108"},{"key":"ref21","first-page":"517","article-title":"Memory diagnosis and built-in self-repair","volume-title":"Proc. VlSI Test Prin. Arch.","author":"Wang"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3337708"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2971481"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2017.2667645"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2010.2049051"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2020.2963911"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD54002.2021.9592547"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/2788396"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2008.917757"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICACCCN.2018.8748495"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISBI.2008.4541126"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2008.57"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2014.7004245"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISPA.2012.132"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ITC44778.2020.9325273"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/66.97808"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/92.285750"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2003.1250090"},{"key":"ref39","volume-title":"Double Data Rate 5 (DDR5)","year":"2022"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10849961\/10679780.pdf?arnumber=10679780","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,23]],"date-time":"2025-01-23T18:54:31Z","timestamp":1737658471000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10679780\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2]]},"references-count":39,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3454286","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,2]]}}}