{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:24:07Z","timestamp":1772119447563,"version":"3.50.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62176206"],"award-info":[{"award-number":["62176206"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Ant Group through CCF-Ant Research Fund","award":["CCF-AFSG RF20230305"],"award-info":[{"award-number":["CCF-AFSG RF20230305"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,2]]},"DOI":"10.1109\/tvlsi.2024.3465010","type":"journal-article","created":{"date-parts":[[2024,10,9]],"date-time":"2024-10-09T17:59:18Z","timestamp":1728496758000},"page":"588-592","source":"Crossref","is-referenced-by-count":4,"title":["A Scalable and Efficient NTT\/INTT Architecture Using Group-Based Pairwise Memory Access and Fast Interstage Reordering"],"prefix":"10.1109","volume":"33","author":[{"given":"Zihang","family":"Wang","sequence":"first","affiliation":[{"name":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"}]},{"given":"Yushu","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-0132-3319","authenticated-orcid":false,"given":"Jianfei","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"}]},{"given":"Jia","family":"Hou","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3619-7936","authenticated-orcid":false,"given":"Yang","family":"Su","sequence":"additional","affiliation":[{"name":"School of Cryptography Engineering, Engineering University of People’s Armed Police, Xi’an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8221-7670","authenticated-orcid":false,"given":"Chen","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Xi’an Jiaotong University, Xi’an, Shaanxi, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nature23461"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1536414.1536440"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19074-2_21"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2633600"},{"key":"ref5","first-page":"144","article-title":"Somewhat practical fully homomorphic encryption","volume-title":"Proc. IACR","author":"Fan"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-70694-8_15"},{"key":"ref7","volume-title":"CRYSTALS-Kyber algorithm specifications and supporting documentation","author":"Avanzi","year":"2020"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3166355"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3289489"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3218192"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3205552"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2022.3184703"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3377366"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.jsc.2013.09.002"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3296492"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3077885"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2922999"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3230359"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10849961\/10710157.pdf?arnumber=10710157","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,23]],"date-time":"2025-01-23T18:55:34Z","timestamp":1737658534000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10710157\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2]]},"references-count":18,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3465010","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,2]]}}}