{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,20]],"date-time":"2026-02-20T18:16:29Z","timestamp":1771611389227,"version":"3.50.1"},"reference-count":53,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62174084"],"award-info":[{"award-number":["62174084"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62341408"],"award-info":[{"award-number":["62341408"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2022YFB4400600"],"award-info":[{"award-number":["2022YFB4400600"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,1]]},"DOI":"10.1109\/tvlsi.2024.3466224","type":"journal-article","created":{"date-parts":[[2024,10,4]],"date-time":"2024-10-04T17:42:23Z","timestamp":1728063743000},"page":"207-220","source":"Crossref","is-referenced-by-count":7,"title":["SPEED: A Scalable RISC-V Vector Processor Enabling Efficient Multiprecision DNN Inference"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0009-0000-2744-8882","authenticated-orcid":false,"given":"Chuanning","family":"Wang","sequence":"first","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University, Nanjing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3430-1189","authenticated-orcid":false,"given":"Chao","family":"Fang","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University, Nanjing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8306-6889","authenticated-orcid":false,"given":"Xiao","family":"Wu","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University, Nanjing, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7227-4786","authenticated-orcid":false,"given":"Zhongfeng","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering, Nanjing University, Nanjing, China"}]},{"given":"Jun","family":"Lin","sequence":"additional","affiliation":[{"name":"School of Electronic Science and Engineering and the Interdisciplinary Research Center for Future Intelligent Chips (Chip-X), Nanjing University, Nanjing, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV48922.2021.00298"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52688.2022.00473"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCSLP49672.2021.9362058"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP43922.2022.9747671"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.48550\/ARXIV.1706.03762"},{"key":"ref6","first-page":"1877","article-title":"Language models are few-shot learners","volume-title":"Proc. Adv. Neural Inf. Process. Syst. (NIPS)","volume":"33","author":"Brown"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP49357.2023.10096223"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS48785.2022.9937659"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2019.00881"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC52403.2022.9712485"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473817"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00982"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2018.8451268"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2018.8465893"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2881913"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2019.01099"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774679"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2865489"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3066572"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/2996864"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.42"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3131581"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2021.3072337"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2018.8445101"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO56248.2022.00080"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3114881"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/OJSSCS.2022.3210082"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3254810"},{"key":"ref30","volume-title":"RISC-V \u2018V\u2019 Vector Extension","author":"Krste","year":"2024"},{"key":"ref31","article-title":"Design of the RISC-V instruction set architecture","author":"Waterman","year":"2016"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP54787.2022.00017"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2023.3292579"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS46773.2023.10181985"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS57931.2023.10198172"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2950087"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3327110"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1609\/aaai.v34i04.5954"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ACPR.2015.7486599"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00474"},{"key":"ref42","article-title":"An image is worth 16\u00d716 words: Transformers for image recognition at scale","volume-title":"Proc. Int. Conf. Learn. Represent. (ICLR)","author":"Dosovitskiy"},{"key":"ref43","first-page":"5753","article-title":"XLNet: Generalized autoregressive pretraining for language understanding","volume-title":"Proc. Adv. Neural Inf. Process. Syst. (NeurIPS)","volume":"32","author":"Yang"},{"key":"ref44","first-page":"13937","article-title":"DynamicViT: Efficient vision transformers with dynamic token sparsification","volume-title":"Proc. Adv. Neural Inf. Process. Syst. (NeurIPS)","volume":"34","author":"Rao"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3197282"},{"key":"ref46","first-page":"30318","article-title":"GPT3.int8(): 8-bit matrix multiplication for transformers at scale","volume-title":"Proc. Adv. Neural Inf. Process. Syst. (NeurIPS)","volume":"35","author":"Dettmers"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3383871"},{"key":"ref48","volume-title":"RISC-V GNU Compiler Toolchain","year":"2020"},{"key":"ref49","volume-title":"RISC-V LLVM Compiler Toolchain","year":"2022"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.4324\/9781410605337-29"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV48922.2021.00060"},{"key":"ref52","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3076987"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.30"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10818617\/10705106.pdf?arnumber=10705106","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,31]],"date-time":"2024-12-31T19:58:13Z","timestamp":1735675093000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10705106\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1]]},"references-count":53,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3466224","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1]]}}}