{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,27]],"date-time":"2025-02-27T05:09:39Z","timestamp":1740632979803,"version":"3.38.0"},"reference-count":30,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"3","license":[{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,3,1]],"date-time":"2025-03-01T00:00:00Z","timestamp":1740787200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001409","name":"Department of Science and Technology (DST) Science and Engineering Research Board (SERB), Government of India (GoI) through Impacting Research Innovation and Technology Round-2","doi-asserted-by":"publisher","award":["IMP\/2018\/001158\/IT"],"award-info":[{"award-number":["IMP\/2018\/001158\/IT"]}],"id":[{"id":"10.13039\/501100001409","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,3]]},"DOI":"10.1109\/tvlsi.2024.3504856","type":"journal-article","created":{"date-parts":[[2024,12,11]],"date-time":"2024-12-11T04:13:06Z","timestamp":1733890386000},"page":"771-779","source":"Crossref","is-referenced-by-count":0,"title":["A Methodology for Datapath Energy Prediction and Optimization in Near Threshold Voltage Regime"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5640-7342","authenticated-orcid":false,"given":"Mahipal","family":"Dargupally","sequence":"first","affiliation":[{"name":"Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6444-8483","authenticated-orcid":false,"given":"Lomash","family":"Chandra Acharya","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9250-9642","authenticated-orcid":false,"given":"Arvind K.","family":"Sharma","sequence":"additional","affiliation":[{"name":"Semiconductor Technology and Systems Department, IMEC, Leuven, Belgium"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4044-1594","authenticated-orcid":false,"given":"Sudeb","family":"Dasgupta","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3986-3730","authenticated-orcid":false,"given":"Anand","family":"Bulusu","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, IIT Roorkee, Roorkee, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1147\/rd.504.0469"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2011.2177004"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2017.2758793"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2005.852162"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228572"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147022"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/iccad.2013.6691155"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ted.2018.2825341"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1984.1052168"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/81.883330"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2010.5724587"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1998.727025"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126611007967"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2035539"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3076202"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2013992"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/225871.225877"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.02.002"},{"key":"ref19","first-page":"211","article-title":"Energy-delay tradeoffs in combinational logic using gate sizing and supply voltage optimization","volume-title":"Proc. ESSCIRC","author":"Stojanovic"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3231173"},{"volume-title":"Downstream slack creation in integrated circuit development","year":"2021","author":"Romain","key":"ref21"},{"volume-title":"Even apportionment based on positive timing slack threshold","year":"2023","author":"Surprise","key":"ref22"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3225551"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2024.3350035"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939890"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3151500"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3040970"},{"volume-title":"Logical Effort: Designing Fast CMOS Circuits","year":"1999","author":"Sutherland","key":"ref28"},{"volume-title":"CMOS VLSI Design: A Circuits and Systems Perspective","year":"2011","author":"Weste","key":"ref29"},{"volume-title":"Synopsys PrimeTime User Guide Version","year":"2016","key":"ref30"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10903148\/10788034.pdf?arnumber=10788034","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,26]],"date-time":"2025-02-26T05:50:43Z","timestamp":1740549043000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10788034\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,3]]},"references-count":30,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3504856","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2025,3]]}}}