{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:23:18Z","timestamp":1772119398592,"version":"3.50.1"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2239033"],"award-info":[{"award-number":["2239033"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,1]]},"DOI":"10.1109\/tvlsi.2024.3507567","type":"journal-article","created":{"date-parts":[[2024,12,4]],"date-time":"2024-12-04T19:26:48Z","timestamp":1733340408000},"page":"128-139","source":"Crossref","is-referenced-by-count":1,"title":["VSAGE: An End-to-End Automated VCO-Based \u0394\u03a3 ADC Generator"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-5349-4006","authenticated-orcid":false,"given":"Ken","family":"Li","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology (GT), Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1391-9422","authenticated-orcid":false,"given":"Tian","family":"Xie","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology (GT), Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2733-0555","authenticated-orcid":false,"given":"Tzu-Han","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology (GT), Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2736-5451","authenticated-orcid":false,"given":"Shaolan","family":"Li","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology (GT), Atlanta, GA, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/dac18072.2020.9218757"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2017.2768826"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/iccad57390.2023.10323720"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/iccad45719.2019.8942060"},{"key":"ref5","first-page":"1","article-title":"INVITED: ALIGN\u2014Open-source analog layout automation from the ground up","volume-title":"Proc. 56th ACM\/IEEE Design Autom. Conf. (DAC)","author":"Kunal"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/dac18074.2021.9586318"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/islped.2019.8824797"},{"key":"ref8","first-page":"51","article-title":"Fully autonomous mixed signal SoC design & layout generation platform","volume-title":"Proc. IEEE Hot Chips Poster 32nd Symp. (HCS)","author":"Ajayi"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/asp-dac52403.2022.9712575"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/iccad51958.2021.9643494"},{"key":"ref11","volume-title":"BC Analog","year":"2024"},{"key":"ref12","volume-title":"Movellus","year":"2024"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2018.2865404"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2822811"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780169"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2022.3228911"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CICC51472.2021.9431521"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2019.8780194"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2948008"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.535416"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062192"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2225738"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2015.7387508"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3105028"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/CICC57935.2023.10121245"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2015.2502166"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.917500"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2693244"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2959479"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/CICC51472.2021.9431499"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2021.3119691"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3104215"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3027666"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3049680"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3089339"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/92\/10818617\/10777924-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10818617\/10777924.pdf?arnumber=10777924","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,31]],"date-time":"2024-12-31T06:32:40Z","timestamp":1735626760000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10777924\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1]]},"references-count":35,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2024.3507567","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1]]}}}