{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,25]],"date-time":"2026-07-25T16:26:52Z","timestamp":1784996812459,"version":"3.55.0"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T00:00:00Z","timestamp":1746057600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T00:00:00Z","timestamp":1746057600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T00:00:00Z","timestamp":1746057600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["92464204"],"award-info":[{"award-number":["92464204"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"Fundamental Research Funds for the Central Universities","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,5]]},"DOI":"10.1109\/tvlsi.2025.3525740","type":"journal-article","created":{"date-parts":[[2025,1,10]],"date-time":"2025-01-10T21:07:38Z","timestamp":1736543258000},"page":"1497-1501","source":"Crossref","is-referenced-by-count":1,"title":["An On-Chip-Training Keyword-Spotting Chip Using Interleaved Pipeline and Computation-in-Memory Cluster in 28-nm CMOS"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9390-4567","authenticated-orcid":false,"given":"Junyi","family":"Qian","sequence":"first","affiliation":[{"name":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6737-7396","authenticated-orcid":false,"given":"Cai","family":"Li","sequence":"additional","affiliation":[{"name":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Long","family":"Chen","sequence":"additional","affiliation":[{"name":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ruidong","family":"Li","sequence":"additional","affiliation":[{"name":"Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Company Ltd., Jinan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tuo","family":"Li","sequence":"additional","affiliation":[{"name":"Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Company Ltd., Jinan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2039-9031","authenticated-orcid":false,"given":"Peng","family":"Cao","sequence":"additional","affiliation":[{"name":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4993-0087","authenticated-orcid":false,"given":"Xin","family":"Si","sequence":"additional","affiliation":[{"name":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5520-1326","authenticated-orcid":false,"given":"Weiwei","family":"Shan","sequence":"additional","affiliation":[{"name":"National ASIC Center, School of Integrated Circuits, Southeast University, Nanjing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365816"},{"key":"ref2","first-page":"1","article-title":"A 1.5 \u03bcW end-to-end keyword spotting SoC with content-adaptive frame sub-sampling and fast-settling analog frontend","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"SeoI"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3197838"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3339528"},{"key":"ref5","first-page":"328","article-title":"0.4 V 988nW time-domain audio feature extraction for keyword spotting using injection-locked oscillators","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Mostafa"},{"key":"ref6","first-page":"330","article-title":"A 1.8% FAR, 2ms decision latency, 1.73 nJ\/decision keywords spotting (KWS) chip incorporating transfer-computing speaker verification, hybrid-domain computing and scalable 5T-SRAM","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Tan"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.106075"},{"issue":"12","key":"ref8","first-page":"4564","article-title":"A 16 nm 140TOPS\/W 5\u03bcJ\/inference keyword spotting engine based on 1D-BCNN","volume":"70","author":"Lin","year":"2023","journal-title":"IEEE Trans. Circuits Syst. II, Exp. Briefs"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454492"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3299855"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3291376"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2942092"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-023-3800-9"},{"key":"ref14","first-page":"568","article-title":"A 16 nm 96Kb integer\/floating-point dual-mode-gain-cell-computing-in-memory macro achieving 73.3\u2013163.3TOPS\/W and 33.2\u201391.2TFLOPS\/W for AI-edge devices","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Khwa"},{"key":"ref15","first-page":"566","article-title":"A 28 nm 83.23TFLOPS\/W POSIT-based compute-in-memory macro for high-accuracy AI applications","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Wang"},{"key":"ref16","first-page":"570","article-title":"A 22 nm 64kb lightning-like hybrid computing-in-memory macro with a compressed adder tree and analog-storage quantizers for transformer and CNNs","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Guo"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3451332"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-021-3407-2"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10977652\/10838343.pdf?arnumber=10838343","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,28]],"date-time":"2025-04-28T17:36:06Z","timestamp":1745861766000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10838343\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5]]},"references-count":18,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3525740","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,5]]}}}