{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,2]],"date-time":"2026-07-02T05:37:30Z","timestamp":1782970650119,"version":"3.54.5"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Scientific Research Programs for High Level Talents of Beijing Smart-Chip Microelectronics Technology Company Ltd","award":["SGSCDT00XPQT2310588"],"award-info":[{"award-number":["SGSCDT00XPQT2310588"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,4]]},"DOI":"10.1109\/tvlsi.2025.3529699","type":"journal-article","created":{"date-parts":[[2025,1,23]],"date-time":"2025-01-23T18:54:22Z","timestamp":1737658462000},"page":"903-915","source":"Crossref","is-referenced-by-count":10,"title":["A Chiplet Platform for Intelligent Radar\/Sonar Leveraging Domain-Specific Reusable Active Interposer"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-9590-8253","authenticated-orcid":false,"given":"Yafei","family":"Liu","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Dejian","family":"Li","sequence":"additional","affiliation":[{"name":"Beijing Smartchip Microelectronics Technology Company Ltd., Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zheng","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chaoqin","family":"Zhang","sequence":"additional","affiliation":[{"name":"Beijing Novauto Technology Co., Ltd., Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yunlai","family":"Zhang","sequence":"additional","affiliation":[{"name":"NewRadio Technologies Co., Ltd., Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0094-8865","authenticated-orcid":false,"given":"Xiangyu","family":"Li","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Beijing National Research Center for Information Science and Technology, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mingwei","family":"Cao","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2309-572X","authenticated-orcid":false,"given":"Shouyi","family":"Yin","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isca52012.2021.00014"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/iccd53106.2021.00069"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/hpca53966.2022.00091"},{"key":"ref4","first-page":"1","article-title":"GIA: A reusable general interposer architecture for agile chiplet integration","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput. Aided Design (ICCAD)","author":"Li"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC32696.2021.00028"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993637"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714998"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3036341"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062957"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HCS55958.2022.9895532"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530428"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.4071\/2380-4505-2019.1.000027"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218539"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSEN.2020.3004252"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.2528\/PIERM18111509"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.3017869"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2897824.2925953"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/L-CA.2007.2"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2013.6522334"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3207195"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-024-01126-y"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED51717.2021.9424296"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960207"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3059228"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2968904"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/EuroSimE54907.2022.9758914"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2023.3264520"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/2966986.2980095"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2830772.2830808"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2017.8203849"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/10937162\/10851388.pdf?arnumber=10851388","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T19:16:35Z","timestamp":1742843795000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10851388\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4]]},"references-count":31,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3529699","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,4]]}}}