{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T05:10:00Z","timestamp":1747977000945,"version":"3.41.0"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,6,1]],"date-time":"2025-06-01T00:00:00Z","timestamp":1748736000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Mediatek Inc."},{"name":"Ministry of Science and Technology, Taiwan","award":["MOST113-2221-E-A49-087"],"award-info":[{"award-number":["MOST113-2221-E-A49-087"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,6]]},"DOI":"10.1109\/tvlsi.2025.3543851","type":"journal-article","created":{"date-parts":[[2025,3,11]],"date-time":"2025-03-11T17:52:54Z","timestamp":1741715574000},"page":"1789-1793","source":"Crossref","is-referenced-by-count":0,"title":["Machine-Learning-Based Ranking of Cell Layout Delay Considering Layout-Dependent Effects"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0213-0162","authenticated-orcid":false,"given":"Ya-Rou","family":"Hsu","sequence":"first","affiliation":[{"name":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8237-0878","authenticated-orcid":false,"given":"Aaron C.-W.","family":"Liang","sequence":"additional","affiliation":[{"name":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Han-Ya","family":"Tsai","sequence":"additional","affiliation":[{"name":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-0136-7558","authenticated-orcid":false,"given":"Yen-Ju","family":"Su","sequence":"additional","affiliation":[{"name":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4623-9941","authenticated-orcid":false,"given":"Charles H.-P.","family":"Wen","sequence":"additional","affiliation":[{"name":"Institute of Electrical and Computer Engineering, National Yang Ming Chiao Tung University, Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hsuan-Ming","family":"Huang","sequence":"additional","affiliation":[{"name":"MediaTek Inc., Hsinchu, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3037885"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2962782"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2022.3179527"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICMTS.2015.7106119"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2022.105449"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2023.3320631"},{"key":"ref7","first-page":"1","article-title":"iTPlace: Machine learning-based delay-aware transistor placement for standard cell synthesis","volume-title":"Proc. 39th Int. Conf. Computer-Aided Design","author":"Lee"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586188"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3569052.3578920"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3626184.3633314"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3167339"},{"key":"ref12","first-page":"315","article-title":"Ranking measures and loss functions in learning to rank","volume-title":"Proc. Adv. Neural Inf. Process. Syst. (NeurIPS)","volume":"22","author":"Chen"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/133160.133199"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1102351.1102363"},{"key":"ref15","first-page":"933","article-title":"An efficient boosting algorithm for combining preferences","volume-title":"Proc. J. Mach. Learn. Res.","volume":"4","author":"Freund"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/1341531.1341544"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1277741.1277809"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1273496.1273513"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11010805\/10922735.pdf?arnumber=10922735","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,23]],"date-time":"2025-05-23T04:28:08Z","timestamp":1747974488000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10922735\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,6]]},"references-count":18,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3543851","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2025,6]]}}}