{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T06:56:32Z","timestamp":1775112992628,"version":"3.50.1"},"reference-count":36,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"name":"DFG through the Project HYBRISC","award":["536099247"],"award-info":[{"award-number":["536099247"]}]},{"name":"DFG through the SPP MemrisTec","award":["422738993"],"award-info":[{"award-number":["422738993"]}]},{"name":"BMBF through the Project KI-IoT","award":["16ME0092"],"award-info":[{"award-number":["16ME0092"]}]},{"name":"BMBF through the Project iCampus II","award":["16ES1128K"],"award-info":[{"award-number":["16ES1128K"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,9]]},"DOI":"10.1109\/tvlsi.2025.3554476","type":"journal-article","created":{"date-parts":[[2025,4,10]],"date-time":"2025-04-10T13:23:06Z","timestamp":1744291386000},"page":"2406-2414","source":"Crossref","is-referenced-by-count":3,"title":["RISC-V CPU Design Using RRAM-CMOS Standard Cells"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2754-7287","authenticated-orcid":false,"given":"Markus","family":"Fritscher","sequence":"first","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0002-8625-2040","authenticated-orcid":false,"given":"Max","family":"Uhlmann","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-0393-2528","authenticated-orcid":false,"given":"Philip","family":"Ostrovskyy","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0212-259X","authenticated-orcid":false,"given":"Daniel","family":"Reiser","sequence":"additional","affiliation":[{"name":"University of Rostock, Rostock, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4413-0937","authenticated-orcid":false,"given":"Junchao","family":"Chen","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-7733-8907","authenticated-orcid":false,"given":"Jianan","family":"Wen","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Carsten","family":"Schulze","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2674-2240","authenticated-orcid":false,"given":"Gerhard","family":"Kahmen","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6077-4732","authenticated-orcid":false,"given":"Dietmar","family":"Fey","sequence":"additional","affiliation":[{"name":"FAU Erlangen Nürnberg, Erlangen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9687-6247","authenticated-orcid":false,"given":"Marc","family":"Reichenbach","sequence":"additional","affiliation":[{"name":"University of Rostock, Rostock, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0267-0203","authenticated-orcid":false,"given":"Milos","family":"Krstic","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3698-2635","authenticated-orcid":false,"given":"Christian","family":"Wenger","sequence":"additional","affiliation":[{"name":"IHP - Leibniz Institut für Innovative Mikroelektronik, Frankfurt an der Oder, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"crossref","first-page":"261","DOI":"10.7551\/mitpress\/12274.003.0027","article-title":"Cramming more components onto integrated circuits (1965)","author":"Moore","year":"2021","journal-title":"Ideas That Created the Future"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/6.591665"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MCSE.2017.29"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2019.2942456"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCT.1971.1083337"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2012.6479146"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2422999"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI61997.2024.00026"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2023.115173"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1186\/s11671-020-03299-9"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1149\/05004.0021ecst"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1063\/1.5108650"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2017.7930176"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1049\/joe.2018.5234"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2954753"},{"issue":"2","key":"ref16","first-page":"210","article-title":"SPICE model of memristor with nonlinear dopant drift","volume":"18","author":"Biolek","year":"2009","journal-title":"Radioengineering"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/SISPAD.2014.6931558"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1039\/c3cp50738f"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2014.2357292"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2750064"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2763171"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342237"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/CNNA.2012.6331426"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID60093.2024.00100"},{"key":"ref25","first-page":"1","article-title":"Experimental verification and evaluation of non-stateful logic gates in resistive RAM","author":"Brackmann","year":"2024","journal-title":"IEEE Trans. Circuits Syst. I, Reg. Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3027693"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CCECE.2016.7726661"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2010.2066530"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2013.2252317"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.35848\/1347-4065\/ac5d86"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1088\/2634-4386\/ac2cd4"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2006.346732"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2008.4796677"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1063\/1.5108654"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2654506"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2912307"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11142529\/10960690.pdf?arnumber=10960690","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:34:16Z","timestamp":1756319656000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10960690\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9]]},"references-count":36,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3554476","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,9]]}}}