{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,10]],"date-time":"2026-10-10T00:53:03Z","timestamp":1791593583058,"version":"4.3.4"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2025,8,1]],"date-time":"2025-08-01T00:00:00Z","timestamp":1754006400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,8,1]],"date-time":"2025-08-01T00:00:00Z","timestamp":1754006400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,8,1]],"date-time":"2025-08-01T00:00:00Z","timestamp":1754006400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012149","name":"National Key Scientific Instrument and Equipment Development Projects of China","doi-asserted-by":"publisher","award":["62027815"],"award-info":[{"award-number":["62027815"]}],"id":[{"id":"10.13039\/501100012149","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62274052"],"award-info":[{"award-number":["62274052"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,8]]},"DOI":"10.1109\/tvlsi.2025.3572112","type":"journal-article","created":{"date-parts":[[2025,6,5]],"date-time":"2025-06-05T13:39:48Z","timestamp":1749130788000},"page":"2104-2117","source":"Crossref","is-referenced-by-count":4,"title":["RHT_NoC: A Reconfigurable Hybrid Topology Architecture for Chiplet-Based Multicore System"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1739-5822","authenticated-orcid":false,"given":"Dongyu","family":"Xu","sequence":"first","affiliation":[{"name":"School of Computer and Information, Anhui Polytechnic University, Wuhu, Anhui, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1688-1151","authenticated-orcid":false,"given":"Wu","family":"Zhou","sequence":"additional","affiliation":[{"name":"School of Computer and Information, Anhui Normal University, Wuhu, Anhui, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8695-4478","authenticated-orcid":false,"given":"Zhengfeng","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Hefei University of Technology, Hefei, Anhui, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0307-7236","authenticated-orcid":false,"given":"Huaguo","family":"Liang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Hefei University of Technology, Hefei, Anhui, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8305-604X","authenticated-orcid":false,"given":"Xiaoqing","family":"Wen","sequence":"additional","affiliation":[{"name":"Department of Creative Informatics, Graduate School of Computer Science and Systems Engineering, Kyushu Institute of Technology, Fukuoka, Japan"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s42514-022-00093-0"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904798"},{"key":"ref3","article-title":"Chiplets and heterogeneous packaging are changing system design and analysis","author":"Park","year":"2020"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2024.3450841"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586261"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530428"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18072.2020.9218539"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070981"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00091"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2023.3321598"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2020.2986297"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00066"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2021.3068615"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2020.106578"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/s44227-024-00046-9"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2024.3477253"},{"key":"ref17","first-page":"1","article-title":"ReSiPI: A reconfigurable silicon-photonic 2.5D chiplet network with PCMs for energy-efficient interposer communication","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput. Aided Design (ICCAD)","author":"Taheri"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137317"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3485585"},{"key":"ref20","first-page":"1","article-title":"GIA: A reusable general interposer architecture for agile chiplet integration","volume-title":"Proc. IEEE\/ACM Int. Conf. Comput. Aided Design (ICCAD)","author":"Li"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3419579"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.23"},{"key":"ref23","volume-title":"Principles and Practices of Interconnection Networks","author":"Dally","year":"2004"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2019.2940190"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2022.10.004"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA51647.2021.00063"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2015.7245728"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2012.31"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1921249.1921258"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2016.7482081"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11096973\/11026095.pdf?arnumber=11026095","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,28]],"date-time":"2025-07-28T19:52:33Z","timestamp":1753732353000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11026095\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8]]},"references-count":31,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3572112","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,8]]}}}