{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,14]],"date-time":"2026-02-14T10:24:24Z","timestamp":1771064664030,"version":"3.50.1"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,9,1]],"date-time":"2025-09-01T00:00:00Z","timestamp":1756684800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Science Foundation of China","doi-asserted-by":"publisher","award":["92464302"],"award-info":[{"award-number":["92464302"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100007219","name":"Natural Science Foundation of Shanghai","doi-asserted-by":"publisher","award":["25ZR1402272"],"award-info":[{"award-number":["25ZR1402272"]}],"id":[{"id":"10.13039\/100007219","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,9]]},"DOI":"10.1109\/tvlsi.2025.3583289","type":"journal-article","created":{"date-parts":[[2025,7,10]],"date-time":"2025-07-10T17:50:56Z","timestamp":1752169856000},"page":"2424-2437","source":"Crossref","is-referenced-by-count":1,"title":["IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D\/2.5-D Multichiplet Systems"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9353-5447","authenticated-orcid":false,"given":"Jinming","family":"Zhang","sequence":"first","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-2318-2619","authenticated-orcid":false,"given":"Zhihong","family":"Chen","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0022-228X","authenticated-orcid":false,"given":"Yaoyao","family":"Ye","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hao","family":"Chen","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiao","family":"Han","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5521-6197","authenticated-orcid":false,"given":"Jianfei","family":"Jiang","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7831-526X","authenticated-orcid":false,"given":"Weiguang","family":"Sheng","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ningyi","family":"Xu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5289-5219","authenticated-orcid":false,"given":"Yong","family":"Lian","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0486-6421","authenticated-orcid":false,"given":"Guanghui","family":"He","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Micro\/Nano Engineering Science, School of Integrated Circuits, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.2968904"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3015494"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3455332"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1987.1676939"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCPMT.2022.3207195"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960488"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1992.753324"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2024.3365954"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774617"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3399660"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3649476.3658704"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00064"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2023.3309742"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2011.5749724"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.3037310"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358255"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA47549.2020.00044"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3458817.3476140"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473948"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00076"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3708543"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2015.2503746"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA56546.2023.10070981"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.23919\/DATE54114.2022.9774519"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2011.63"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.44"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.1995.524561"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00066"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3029682"},{"key":"ref30","first-page":"46","article-title":"ASDR: An application-specific deadlock-free routing for chiplet-based systems","volume-title":"Proc. 16th Int. Workshop Netw. Chip Architectures","author":"Ye"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.2016.201"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2014.7047117"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2873584"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3419579"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3036341"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530428"},{"key":"ref37","volume-title":"AIB-Specification","year":"2020"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.3040410"},{"key":"ref39","volume-title":"Advanced Cost-Driven Chiplet Interface (ACC) 1.0","year":"2024"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2012.6169049"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.080"},{"key":"ref42","volume-title":"The Gem5 Simulator","year":"2011"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11142529\/11076167.pdf?arnumber=11076167","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,8,27]],"date-time":"2025-08-27T18:34:13Z","timestamp":1756319653000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11076167\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,9]]},"references-count":42,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3583289","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,9]]}}}