{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,23]],"date-time":"2026-10-23T20:51:17Z","timestamp":1792788677723,"version":"4.5.0"},"reference-count":19,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Wallenberg AI Autonomous Systems and Software (WASP) Program through the Knut and Alice Wallenberg Foundation"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,11]]},"DOI":"10.1109\/tvlsi.2025.3591522","type":"journal-article","created":{"date-parts":[[2025,8,4]],"date-time":"2025-08-04T18:48:21Z","timestamp":1754333301000},"page":"2929-2939","source":"Crossref","is-referenced-by-count":4,"title":["SGRACE: Scalable Architecture for On-Device Inference and Training of Graph Attention and Convolutional Networks"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5153-5481","authenticated-orcid":false,"given":"Jose","family":"Nunez-Yanez","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Linköping University, Linköping, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Hadi","family":"Mousanejad Jeddi","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Linköping University, Linköping, Sweden"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.2172\/1821960"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3447548.3467350"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/hpca56546.2023.10071015"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP49362.2020.00019"},{"key":"ref5","doi-asserted-by":"crossref","DOI":"10.1016\/j.sysarc.2022.102596","article-title":"QEGCN: An FPGA-based accelerator for quantized GCNs with edge-level parallelism","volume":"129","author":"Yuan","year":"2022","journal-title":"J. Syst. Archit."},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00079"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/fpl57034.2022.00040"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480113"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3373087.3375312"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/HPEC55821.2022.9926312"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3490422.3502359"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL60245.2023.00037"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-86362-3_21"},{"key":"ref14","article-title":"Graph attention networks","author":"Veli\u010dkovi\u0107","year":"2017","journal-title":"arXiv:1710.10903"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/NorCAS64408.2024.10752486"},{"key":"ref16","article-title":"A white paper on neural network quantization","author":"Nagel","year":"2021","journal-title":"arXiv:2106.08295"},{"key":"ref17","article-title":"Degree-quant: Quantization-aware training for graph neural networks","author":"Tailor","year":"2020","journal-title":"arXiv:2008.05000"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2013.0117"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/NorCAS64408.2024.10752483"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11222394\/11108959.pdf?arnumber=11108959","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T05:37:12Z","timestamp":1761889032000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11108959\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11]]},"references-count":19,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3591522","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,11]]}}}