{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,30]],"date-time":"2025-12-30T18:53:23Z","timestamp":1767120803795,"version":"3.48.0"},"reference-count":33,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T00:00:00Z","timestamp":1767225600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62204199"],"award-info":[{"award-number":["62204199"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Key Research and Development Projects","doi-asserted-by":"publisher","award":["2019YFB2204702"],"award-info":[{"award-number":["2019YFB2204702"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2026,1]]},"DOI":"10.1109\/tvlsi.2025.3600894","type":"journal-article","created":{"date-parts":[[2025,8,26]],"date-time":"2025-08-26T19:25:14Z","timestamp":1756236314000},"page":"83-92","source":"Crossref","is-referenced-by-count":0,"title":["A Cryo-Tolerant &gt;40-dB IRR, 4.7\u20137.9-GHz Double Quadrature Cryo-CMOS Receiver With a Broadband LNA for Scalable Quantum Applications"],"prefix":"10.1109","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-4850-4896","authenticated-orcid":false,"given":"Zixun","family":"Gao","sequence":"first","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8800-9920","authenticated-orcid":false,"given":"Chenglong","family":"Liang","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"given":"Ruixin","family":"Liang","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"given":"Suyuan","family":"Gan","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5563-9504","authenticated-orcid":false,"given":"Bingjun","family":"Tang","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"given":"Xingguo","family":"Dong","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"given":"Ya","family":"Zhao","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6682-7084","authenticated-orcid":false,"given":"Youze","family":"Xin","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"given":"Bing","family":"Zhang","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4002-9281","authenticated-orcid":false,"given":"Li","family":"Geng","sequence":"additional","affiliation":[{"name":"Shaanxi Provincial Key Laboratory of Electronic Devices and Advanced Chips, Xi&#x2019;an Key Laboratory of Micro-Nano Electronics and System Integration, School of Microelectronics, Xi&#x2019;an Jiaotong University, Xi&#x2019;an, China"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TQE.2022.3174017"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2737549"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ESSERC62670.2024.10719580"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365848"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365758"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3198663"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/cicc57935.2023.10121300"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2024.3456111"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454392"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49661.2025.10904808"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS56072.2025.11044152"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2014.211"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-024-07160-2"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3430079"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.917990"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3073068"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1103\/PhysRevA.110.052408"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1002\/9781118438046"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ictta.2008.4530240"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/4.482196"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JEDS.2020.2986722"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/tcsii.2024.3386843"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.2986645"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2017.2760834"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2010.2041570"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/tmtt.2025.3554820"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2021.3074160"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2799983"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2015.2496187"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2010.2041575"},{"volume-title":"Design of Integrated Circuits for Optical Communications","year":"2025","author":"Author","key":"ref31"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2018.2881795"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/rfic54546.2022.9863208"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11318092\/11142466.pdf?arnumber=11142466","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,30]],"date-time":"2025-12-30T18:40:15Z","timestamp":1767120015000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11142466\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,1]]},"references-count":33,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3600894","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2026,1]]}}}