{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T07:13:17Z","timestamp":1761894797105,"version":"build-2065373602"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T00:00:00Z","timestamp":1761955200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2025,11]]},"DOI":"10.1109\/tvlsi.2025.3600965","type":"journal-article","created":{"date-parts":[[2025,8,28]],"date-time":"2025-08-28T18:12:10Z","timestamp":1756404730000},"page":"2940-2951","source":"Crossref","is-referenced-by-count":0,"title":["Hybrid SORN Cross-Correlation Architecture for Low-Complexity FPGAs"],"prefix":"10.1109","volume":"33","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1345-076X","authenticated-orcid":false,"given":"Jochen","family":"Rust","sequence":"first","affiliation":[{"name":"Hamburg University of Applied Sciences (HAW Hamburg), Hamburg, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8214-7636","authenticated-orcid":false,"given":"Moritz","family":"B\u00e4rthel","sequence":"additional","affiliation":[{"name":"Institute for Electrodynamics and Microelectronics (ITEM.me), University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nils","family":"H\u00fclsmeier","sequence":"additional","affiliation":[{"name":"Institute for Electrodynamics and Microelectronics (ITEM.me), University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Steffen","family":"Paul","sequence":"additional","affiliation":[{"name":"Institute for Electrodynamics and Microelectronics (ITEM.me), University of Bremen, Bremen, Germany"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"volume-title":"Computer Arithmetic: Algorithms and Hardware Designs","year":"2010","author":"Parhami","key":"ref1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1201\/9781003466024"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.034"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/RusAutoCon61949.2024.10694320"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/I2CT57861.2023.10126491"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2019.2939429"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.14529\/jsfi160203"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3091778"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2020.2983709"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-32180-1_7"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-32180-1_5"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IEEECONF60004.2024.10942961"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/NEWCAS52662.2022.9841985"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/PIMRC.2012.6362738"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511805172"},{"key":"ref16","article-title":"A primer on Zadoff Chu sequences","author":"Andrews","year":"2022","journal-title":"arXiv:2211.05702"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/Eusipco47968.2020.9287466"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ICDSP.2018.8631662"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/s11155-006-7220-9"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ieeestd.2019.8938196"},{"volume-title":"Advanced Micro Devices","year":"2025","key":"ref21"},{"volume-title":"GateMate FPGA Datasheet","year":"2025","key":"ref22"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1017\/CBO9780511754661"},{"key":"ref24","first-page":"209","article-title":"Orthogonal frequency division multiple access wireless communications","author":"Parker","year":"2017","journal-title":"Digital Signal Processing 101 (Second Edition)"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS202256217.2022.9970970"},{"volume-title":"Kintex 7","year":"2025","author":"Micro Devices","key":"ref26"},{"volume-title":"Low-Power CMOS VLSI Circuit Design","year":"2000","author":"Roy","key":"ref27"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11222394\/11143590.pdf?arnumber=11143590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T05:36:13Z","timestamp":1761888973000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11143590\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11]]},"references-count":27,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3600965","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"type":"print","value":"1063-8210"},{"type":"electronic","value":"1557-9999"}],"subject":[],"published":{"date-parts":[[2025,11]]}}}