{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,25]],"date-time":"2026-01-25T11:43:05Z","timestamp":1769341385491,"version":"3.49.0"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T00:00:00Z","timestamp":1769904000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T00:00:00Z","timestamp":1769904000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,1]],"date-time":"2026-02-01T00:00:00Z","timestamp":1769904000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2026,2]]},"DOI":"10.1109\/tvlsi.2025.3625215","type":"journal-article","created":{"date-parts":[[2025,11,11]],"date-time":"2025-11-11T18:30:54Z","timestamp":1762885854000},"page":"352-365","source":"Crossref","is-referenced-by-count":0,"title":["12-bit SAR ADC Employing a 9-bit CDAC in Vanilla CMOS 40-nm Technology"],"prefix":"10.1109","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1356-4254","authenticated-orcid":false,"given":"Amr W.","family":"Hassan","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6938-9083","authenticated-orcid":false,"given":"Shangfeng","family":"Qiu","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7960-0177","authenticated-orcid":false,"given":"Jose","family":"Silva-Martinez","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067498"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2015.7438014"},{"key":"ref3","doi-asserted-by":"crossref","DOI":"10.1109\/TCSI.2025.3605848","article-title":"A 700 MS\/s 12-bit pipeline-ADC with a sub-range 6-bit back-end achieving 79 dB signal-to-distortion ratio and FoM of 170.1 dB near Nyquist frequency","author":"Qiu","year":"2025","journal-title":"IEEE Trans. Circuits Syst. I, Reg. Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3166792"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2013.6649084"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662524"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2017.7870463"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662299"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008491"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLDI-DAT.2013.6533842"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2005.1464555"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2007.4425772"},{"key":"ref13","first-page":"236","article-title":"A 0.92mW 10-bit 50-MS\/s SAR ADC in 0.13m CMOS process","volume-title":"Proc. Symp. VLSI Circuits","author":"Liu"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3322633"},{"key":"ref15","volume-title":"Fundamentals of Precision ADC Noise Analysis","year":"2020"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2020.3036143"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373420"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2017.2756036"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2466475"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/4.16303"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/vlsic.2014.6858453"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008506"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231329"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2981971"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2946215"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11361320\/11239468.pdf?arnumber=11239468","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,1,23]],"date-time":"2026-01-23T21:02:22Z","timestamp":1769202142000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11239468\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2]]},"references-count":26,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2025.3625215","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,2]]}}}