{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T20:08:11Z","timestamp":1780344491103,"version":"3.54.1"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,5,1]],"date-time":"2026-05-01T00:00:00Z","timestamp":1777593600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62274068"],"award-info":[{"award-number":["62274068"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2024YFB4505400"],"award-info":[{"award-number":["2024YFB4505400"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2026,5]]},"DOI":"10.1109\/tvlsi.2026.3663605","type":"journal-article","created":{"date-parts":[[2026,2,23]],"date-time":"2026-02-23T20:50:54Z","timestamp":1771879854000},"page":"1672-1676","source":"Crossref","is-referenced-by-count":0,"title":["TRO-Based Dual-Domain Voltage Co-Regulation of Digital Logic and SRAM in SoCs"],"prefix":"10.1109","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0009-0001-9251-4046","authenticated-orcid":false,"given":"Zhaoxu","family":"Wang","sequence":"first","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-1149-7219","authenticated-orcid":false,"given":"Xi","family":"Deng","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mingyang","family":"Gong","sequence":"additional","affiliation":[{"name":"Xi'an FANYI University, Xi'an, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-8191-0061","authenticated-orcid":false,"given":"Zhenhao","family":"Li","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-9806-3559","authenticated-orcid":false,"given":"Runze","family":"Yu","sequence":"additional","affiliation":[{"name":"Wuhan Top-AI semiconductor Company Ltd., Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1546-3417","authenticated-orcid":false,"given":"Zhenglin","family":"Liu","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6404-5270","authenticated-orcid":false,"given":"Xuecheng","family":"Zou","sequence":"additional","affiliation":[{"name":"School of Integrated Circuits, Huazhong University of Science and Technology, Wuhan, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2025.3592906"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/iscas56072.2025.11043289"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2024.3409315"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/tvlsi.2024.3510697"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2023.3347469"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSICircuits18222.2020.9162790"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063136"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2023.3257270"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032493"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.2010101"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3367233"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.823443"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4614-8881-1"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914720"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11538104\/11405435.pdf?arnumber=11405435","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T19:37:57Z","timestamp":1780342677000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11405435\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,5]]},"references-count":14,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2026.3663605","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,5]]}}}