{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T20:11:28Z","timestamp":1780517488203,"version":"3.54.1"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T00:00:00Z","timestamp":1780272000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T00:00:00Z","timestamp":1780272000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,6,1]],"date-time":"2026-06-01T00:00:00Z","timestamp":1780272000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"Semiconductor Research Corporation (SRC) Logic and Memory Devices (LMD) under Project 3239"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2026,6]]},"DOI":"10.1109\/tvlsi.2026.3678304","type":"journal-article","created":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T20:09:53Z","timestamp":1775678993000},"page":"1848-1856","source":"Crossref","is-referenced-by-count":0,"title":["Metal Stack Exploration for Front- Versus Back- Side Clock and Signal Allocation for Advanced CMOS PPA Improvements"],"prefix":"10.1109","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-0235-8185","authenticated-orcid":false,"given":"Nishant","family":"Gupta","sequence":"first","affiliation":[{"name":"Chandra Family Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2895-3159","authenticated-orcid":false,"given":"Sirish","family":"Oruganti","sequence":"additional","affiliation":[{"name":"Chandra Family Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6733-1910","authenticated-orcid":false,"given":"Sai Subrahmanya Teja","family":"Nibhanupudi","sequence":"additional","affiliation":[{"name":"Chandra Family Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0000-9213-4468","authenticated-orcid":false,"given":"Anup Ashok","family":"Kedilaya","sequence":"additional","affiliation":[{"name":"Chandra Family Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0489-0197","authenticated-orcid":false,"given":"Xiuhao","family":"Zhang","sequence":"additional","affiliation":[{"name":"Chandra Family Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0258-6776","authenticated-orcid":false,"given":"Jaydeep P.","family":"Kulkarni","sequence":"additional","affiliation":[{"name":"Chandra Family Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir57934.2023.10185211"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/vlsitechnologyandcir46769.2022.9830177"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir57934.2023.10185302"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/iedm19573.2019.8993617"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185417"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/islped58423.2023.10244504"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir57934.2023.10185319"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631449"},{"key":"ref9","first-page":"1","article-title":"Demonstration of a stacked CMOS inverter at 60 nm gate pitch with power via and direct backside device contacts","author":"Radosavljevi\u0107","year":"2023","journal-title":"IEDM Tech. Dig."},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631556"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ectc32862.2020.00020"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ectc51906.2022.00244"},{"key":"ref13","volume-title":"IMEC 2025 Technology Roadmap","year":"2025"},{"key":"ref14","volume-title":"LowRISC, Low RISC Open Source Ibex","year":"2024"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ectc51909.2023.00334"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/vlsitechnologyandcir46783.2024.10631379"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"key":"ref18","volume-title":"TSMC Unveils 1.6nm Process Technology With Backside Power Delivery, Rivals Intel\u2019s Competing Design","author":"Shilov"},{"key":"ref19","volume-title":"Samsung Foundry Unveils Roadmap for 2nm and BSPDN Through 2027","author":"Shilov"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir57934.2023.10185369"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir57934.2023.10185208"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2016.2572144"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/mm.2020.2995854"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/mc.2022.3174253"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/iedm.2017.8268472"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2018.8614662"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.23919\/VLSITechnologyandCir65189.2025.11075006"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/vlsit.2018.8510618"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/jxcdc.2025.3617784"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11547350\/11477130.pdf?arnumber=11477130","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T19:46:23Z","timestamp":1780515983000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11477130\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,6]]},"references-count":29,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2026.3678304","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,6]]}}}