{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,28]],"date-time":"2026-07-28T05:01:08Z","timestamp":1785214868769,"version":"3.55.0"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,8,1]],"date-time":"2026-08-01T00:00:00Z","timestamp":1785542400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Trans. VLSI Syst."],"published-print":{"date-parts":[[2026,8]]},"DOI":"10.1109\/tvlsi.2026.3694263","type":"journal-article","created":{"date-parts":[[2026,6,24]],"date-time":"2026-06-24T19:53:03Z","timestamp":1782330783000},"page":"2537-2544","source":"Crossref","is-referenced-by-count":0,"title":["ENLIVEN: End-to-End NPU--ISP Codesign for Low-Latency and Hardware-Optimized Visual Processing"],"prefix":"10.1109","volume":"34","author":[{"ORCID":"https:\/\/orcid.org\/0009-0008-9935-5261","authenticated-orcid":false,"given":"Jiangtao","family":"Cui","sequence":"first","affiliation":[{"name":"Tsinghua University","place":["Beijing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xinyu","family":"Shao","sequence":"additional","affiliation":[{"name":"Tsinghua University","place":["Beijing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2170-2602","authenticated-orcid":false,"given":"Sheng","family":"Zhang","sequence":"additional","affiliation":[{"name":"Tsinghua University","place":["Beijing, China"]}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCC58585.2023.10256910"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00011"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3368350"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC62682.2024.10762715"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR46437.2021.00622"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52733.2024.02463"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA61900.2025.00028"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/CVPRW50498.2020.00276"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.23919\/DATE56975.2023.10137196"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.23919\/DATE64628.2025.10993256"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.23919\/ICCAS63016.2024.10773198"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2023.3305016"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/esscirc55480.2022.9911509"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITSA60681.2024.10546413"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2024.3510939"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00052"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR42600.2020.00755"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CVPRW53098.2021.00284"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CCAI57533.2023.10201248"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52688.2022.00555"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52734.2025.02356"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52729.2023.01863"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ICCV51070.2023.00371"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC55480.2022.9911515"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492338"}],"container-title":["IEEE Transactions on Very Large Scale Integration (VLSI) Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/92\/11626298\/11577180.pdf?arnumber=11577180","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,7,28]],"date-time":"2026-07-28T04:38:12Z","timestamp":1785213492000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11577180\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,8]]},"references-count":25,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/tvlsi.2026.3694263","relation":{},"ISSN":["1063-8210","1557-9999"],"issn-type":[{"value":"1063-8210","type":"print"},{"value":"1557-9999","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,8]]}}}