{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T06:21:40Z","timestamp":1729664500309,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/uemcon.2016.7777928","type":"proceedings-article","created":{"date-parts":[[2016,12,12]],"date-time":"2016-12-12T20:35:39Z","timestamp":1481574939000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["JSM gate \u2014 A new proposition in spin based reversible logic circuitry"],"prefix":"10.1109","author":[{"given":"J.","family":"Gope","sequence":"first","affiliation":[]},{"given":"S.","family":"Chowdhury","sequence":"additional","affiliation":[]},{"given":"K. S.","family":"Ghosal","sequence":"additional","affiliation":[]},{"given":"K.","family":"Sarkar","sequence":"additional","affiliation":[]},{"given":"M.","family":"Pal","sequence":"additional","affiliation":[]},{"given":"S.","family":"Bhadra","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"207","article-title":"Modified Toffoli gate and its applications in designing components of reversible arithmetic and logic unit","volume":"2","author":"jayashree","year":"2012","journal-title":"International Journal of Advanced Research in Computer Science and Software Engineering"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/NANO.2011.6144350"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/TIM.2006.870319"},{"key":"ref13","first-page":"411","article-title":"Reversible programmable logic array (RPLA) using Feynman & MUX gates for low power industrial application","author":"singhla","year":"2012","journal-title":"1st International Conference on Innovations and Advancements in Information and Communication Technology"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.4236\/cs.2014.51002"},{"year":"2009","author":"saiful islam","article-title":"Synthesis of fault tolerant reversible logic circuit","key":"ref15"},{"key":"ref16","first-page":"16","article-title":"A hypothetical approach of designing novel reversible combinational logic","author":"gope","year":"2016","journal-title":"IOSR Journal of Mechanical and Civil Engineering"},{"year":"0","author":"gope","article-title":"Single Spin Modelling of Reversible Logic Gates","key":"ref17"},{"key":"ref4","first-page":"2279","article-title":"VHDL implementation of 4-bit full adder using reversible logic gates","volume":"1","author":"patel","year":"0","journal-title":"International Journal for Scientific Research & Development"},{"key":"ref3","first-page":"3838","article-title":"An improved design of a multiplier using reversible logic gates","volume":"2","author":"bhagyalakshmi","year":"2010","journal-title":"International Journal of Engineering Science and Technology"},{"key":"ref6","first-page":"496","article-title":"An optimized realization of ALU for 12-operations by using a control unit of reversible gates","volume":"4","author":"mamataj","year":"2014","journal-title":"International Journal of Advanced Research in Computer Science and Software Engineering"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"132","DOI":"10.17812\/IJRA.1.3(27)2014","article-title":"Energy efficient reversible logic design for code converters","volume":"1","author":"kamani","year":"2014","journal-title":"International journal research and application"},{"key":"ref8","first-page":"595","article-title":"Spintronics device based power efficient VLSI chip design for universal code converter","volume":"2","author":"sarkar","year":"0","journal-title":"Canadian Journal of pure & applied science SENRA Academic Publishers Burnaby British Columbia"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"537","DOI":"10.1109\/5.752515","article-title":"Nanoscale CMOS","volume":"87","author":"wong","year":"2002","journal-title":"IEEE Proceedings"},{"key":"ref2","first-page":"417","article-title":"A review on reversible logic gates and their implementation","volume":"3","author":"garipelly","year":"2013","journal-title":"Int J of Emerging Tech and Advanced Eng"},{"key":"ref1","article-title":"Introduction to reversible logic gates & its application","author":"yelekar","year":"2011","journal-title":"2nd National Conference on Information and Communication Technology (NCICT) Proceedings published in International Journal of Computer Applications&#x00AE; (IJCA) Proc"},{"key":"ref9","first-page":"146","article-title":"Exploration of Single Spin Logic (SSL) Based Expandable Hardware Design","volume":"7","author":"jayanta gope","year":"2013","journal-title":"IJSER"}],"event":{"name":"2016 IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)","start":{"date-parts":[[2016,10,20]]},"location":"New York City, NY, USA","end":{"date-parts":[[2016,10,22]]}},"container-title":["2016 IEEE 7th Annual Ubiquitous Computing, Electronics &amp; Mobile Communication Conference (UEMCON)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7763653\/7777798\/07777928.pdf?arnumber=7777928","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,25]],"date-time":"2017-06-25T01:46:57Z","timestamp":1498355217000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7777928\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/uemcon.2016.7777928","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}