{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T21:59:54Z","timestamp":1725659994837},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,9,16]]},"DOI":"10.1109\/vdat53777.2021.9600953","type":"proceedings-article","created":{"date-parts":[[2021,11,10]],"date-time":"2021-11-10T23:41:04Z","timestamp":1636587664000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Analytical Modelling of a CMOS Inter Spike Interval Decoder for Resistive Crossbar based Brain Inspired Computing"],"prefix":"10.1109","author":[{"given":"Sahibia Kaur","family":"Vohra","sequence":"first","affiliation":[]},{"given":"Sherin","family":"Thomas","sequence":"additional","affiliation":[]},{"given":"Mahendra","family":"Sakare","sequence":"additional","affiliation":[]},{"given":"Devarshi Mrinal","family":"Das","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1016\/j.tins.2009.12.001"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2019.2933719"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2683260"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2017.2765892"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2738040"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2019.2899262"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2533298"}],"event":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2021,9,16]]},"location":"Surat, India","end":{"date-parts":[[2021,9,18]]}},"container-title":["2021 25th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9600867\/9600899\/09600953.pdf?arnumber=9600953","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:50:52Z","timestamp":1652201452000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9600953\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,16]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/vdat53777.2021.9600953","relation":{},"subject":[],"published":{"date-parts":[[2021,9,16]]}}}