{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,26]],"date-time":"2025-11-26T16:38:38Z","timestamp":1764175118159,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,9,16]]},"DOI":"10.1109\/vdat53777.2021.9601025","type":"proceedings-article","created":{"date-parts":[[2021,11,10]],"date-time":"2021-11-10T18:41:04Z","timestamp":1636569664000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["A Hardware Generator for Posit Arithmetic and its FPGA Prototyping"],"prefix":"10.1109","author":[{"given":"Diksha","family":"Shekhawat","sequence":"first","affiliation":[]},{"given":"Apoorva","family":"Jangir","sequence":"additional","affiliation":[]},{"given":"Jai Gopal","family":"Pandey","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2920936"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s40031-019-00418-8"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/SIECPC.2011.5876905"},{"key":"ref13","article-title":"Posit arithmetic","volume":"30","author":"gustafson","year":"2017","journal-title":"Mathematica Notebook describing the posit number system"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.23919\/EETA.2018.8493233"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2018.8342187"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/s10617-021-09252-y"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2018.1540065"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS47924.2020.00069"},{"key":"ref5","first-page":"71","article-title":"Beating floating point at its own game: Posit arithmetic","volume":"4","author":"gustafson","year":"2017","journal-title":"Supercomputing Frontiers and Innovations"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2018.00057"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2018.8351142"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1117\/12.787408"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/DATE48585.2020.9116196"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED51717.2021.9424360"}],"event":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2021,9,16]]},"location":"Surat, India","end":{"date-parts":[[2021,9,18]]}},"container-title":["2021 25th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9600867\/9600899\/09601025.pdf?arnumber=9601025","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T12:50:52Z","timestamp":1652187052000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9601025\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,16]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/vdat53777.2021.9601025","relation":{},"subject":[],"published":{"date-parts":[[2021,9,16]]}}}