{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T08:00:43Z","timestamp":1761897643124,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,9,16]]},"DOI":"10.1109\/vdat53777.2021.9601075","type":"proceedings-article","created":{"date-parts":[[2021,11,10]],"date-time":"2021-11-10T23:41:04Z","timestamp":1636587664000},"page":"1-4","source":"Crossref","is-referenced-by-count":3,"title":["High Speed and Power Efficient Multiplexer based Matrix Vector Multiplication for LSTM Network"],"prefix":"10.1109","author":[{"given":"Tresa","family":"Joseph","sequence":"first","affiliation":[]},{"given":"T. S.","family":"Bindiya","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2004.1333283"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2018.2858362"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3174243.3174253"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2856513"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3337929"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2941921"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2019.2936761"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2012.2205597"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3097264"},{"key":"ref5","first-page":"181","article-title":"FPGA-Based Design and Realization of Fixed and Floating Point Matrix Multipliers: A Review","volume":"5","author":"qasim","year":"2010","journal-title":"J of Active and Passive Electronic Devices"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2717950"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2926482"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-24797-2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2020.2982416"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2947639"}],"event":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2021,9,16]]},"location":"Surat, India","end":{"date-parts":[[2021,9,18]]}},"container-title":["2021 25th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9600867\/9600899\/09601075.pdf?arnumber=9601075","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:50:51Z","timestamp":1652201451000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9601075\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,16]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/vdat53777.2021.9601075","relation":{},"subject":[],"published":{"date-parts":[[2021,9,16]]}}}