{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,19]],"date-time":"2026-02-19T03:32:09Z","timestamp":1771471929349,"version":"3.50.1"},"reference-count":16,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,9,16]],"date-time":"2021-09-16T00:00:00Z","timestamp":1631750400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,9,16]]},"DOI":"10.1109\/vdat53777.2021.9601129","type":"proceedings-article","created":{"date-parts":[[2021,11,10]],"date-time":"2021-11-10T23:41:04Z","timestamp":1636587664000},"page":"1-4","source":"Crossref","is-referenced-by-count":11,"title":["Performance Comparison of Single Level STT and SOT MRAM Cells for Cache Applications"],"prefix":"10.1109","author":[{"given":"Ashish","family":"Sura","sequence":"first","affiliation":[]},{"given":"Vikas","family":"Nehra","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/j.jmmm.2020.166711"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1108\/CW-04-2019-0036"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.mattod.2017.07.007"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1038\/nmat3279"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1126\/science.1218197"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2019.2940581"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2018.2875491"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2016.2590142"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TMAG.2010.2042041"},{"key":"ref6","first-page":"233","article-title":"Spintronics Memory and Logic: An Efficient Alternative to CMOS Technology","author":"nehra","year":"2019","journal-title":"VLSI and Post-CMOS Electronics Volume 1 Design Modelling and Simulations"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2015.7168558"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2027907"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1038\/nmat2804"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547704"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2017.2762699"}],"event":{"name":"2021 25th International Symposium on VLSI Design and Test (VDAT)","location":"Surat, India","start":{"date-parts":[[2021,9,16]]},"end":{"date-parts":[[2021,9,18]]}},"container-title":["2021 25th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9600867\/9600899\/09601129.pdf?arnumber=9601129","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,10]],"date-time":"2022-05-10T16:50:51Z","timestamp":1652201451000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9601129\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,9,16]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/vdat53777.2021.9601129","relation":{},"subject":[],"published":{"date-parts":[[2021,9,16]]}}}