{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,13]],"date-time":"2025-09-13T16:29:15Z","timestamp":1757780955529,"version":"3.27.0"},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,9,1]]},"DOI":"10.1109\/vdat63601.2024.10705674","type":"proceedings-article","created":{"date-parts":[[2024,10,9]],"date-time":"2024-10-09T17:45:58Z","timestamp":1728495958000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":["Innovative Circuit Level Methodology for FinFET based Low-Power 6T SRAM Cell Design"],"prefix":"10.1109","author":[{"given":"Vishal","family":"Gupta","sequence":"first","affiliation":[{"name":"Vellore Institute of Technology,School of Electronics Engineering,Vellore,Tamil Nadu,India"}]},{"given":"Sribhuvaneshwari","family":"H","sequence":"additional","affiliation":[{"name":"Sri Shakthi Institute of Engineering and Technology,Dept. of Electronics and Communication Engineering,Coimbatore,Tamil Nadu,India"}]},{"given":"Tanmaya Kumar","family":"Das","sequence":"additional","affiliation":[{"name":"Vellore Institute of Technology,School of Electronics Engineering,Vellore,Tamil Nadu,India"}]},{"given":"Saurabh","family":"Khandelwal","sequence":"additional","affiliation":[{"name":"Oxford Brookes University,School of ECM,Oxford,United Kingdom"}]},{"given":"Shyam","family":"Akashe","sequence":"additional","affiliation":[{"name":"ITM University,Dept. of Electronics & Communication Engineering,Gwalior,Madhya Pradesh,India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MCAS.2011.942068"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DTIS.2018.8368553"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/NUICONE.2015.7449596"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1166\/jno.2015.1843"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2014.2365963"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/dac.2002.1012673"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2018.8602981"}],"event":{"name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2024,9,1]]},"location":"Vellore, India","end":{"date-parts":[[2024,9,3]]}},"container-title":["2024 28th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10705646\/10705432\/10705674.pdf?arnumber=10705674","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,16]],"date-time":"2024-10-16T17:50:03Z","timestamp":1729101003000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10705674\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,1]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/vdat63601.2024.10705674","relation":{},"subject":[],"published":{"date-parts":[[2024,9,1]]}}}