{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T15:32:42Z","timestamp":1730302362199,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,9,1]]},"DOI":"10.1109\/vdat63601.2024.10705730","type":"proceedings-article","created":{"date-parts":[[2024,10,9]],"date-time":"2024-10-09T17:45:58Z","timestamp":1728495958000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["MATLAB-Simulink based Framework for Combinational ATPG Applied to Testing of Digital Blocks in Analog and Mixed-Signal Circuits"],"prefix":"10.1109","author":[{"given":"Puja","family":"Kumari","sequence":"first","affiliation":[{"name":"Indian Institute of Technology (ISM),Department of Electronics Engineering,Dhanbad,India"}]},{"given":"Rahul","family":"Bhattacharya","sequence":"additional","affiliation":[{"name":"Indian Institute of Technology (ISM),Department of Electronics Engineering,Dhanbad,India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ADCOM.2007.119"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1999.805626"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766682"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2016.7482474"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s10836-023-06088-1"},{"article-title":"Fan: A fanout-oriented test pattern generation algorithm","volume-title":"Proc. IEEE International Symposium on Circuits and Systems","author":"Fujiwara","key":"ref6"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.1993.398789"},{"volume-title":"Digital Integrated Circuits: Design-for-Test Using Simulink\u00ae and Stateflow\u00ae","year":"2018","author":"Evgeni","key":"ref8"},{"volume-title":"Introduction to Simulink with engineering applications","year":"2006","author":"Karris","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.35940\/ijeat.B3565.129219"},{"article-title":"Multiple Feedback Band-Pass Design Example","volume-title":"Analog Devices\u2019s Mini Tutorial # MT-218.","author":"Zumbahlen","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008349817903"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-22577-2_31"},{"key":"ref14","article-title":"Implementation of an ATPG using PODEM (path oriented decision making) algorithm","volume-title":"Foundations of VLSI CAD course project","author":"Joshi","year":"2016"},{"key":"ref15","volume-title":"Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits","volume":"17","author":"Bushnell","year":"2004"},{"volume-title":"ISCAS 85 Benchmark Circuits","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1016\/j.measurement.2012.04.022"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CODEC.2015.7893197"}],"event":{"name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2024,9,1]]},"location":"Vellore, India","end":{"date-parts":[[2024,9,3]]}},"container-title":["2024 28th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10705646\/10705432\/10705730.pdf?arnumber=10705730","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T11:45:13Z","timestamp":1728560713000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10705730\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,1]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/vdat63601.2024.10705730","relation":{},"subject":[],"published":{"date-parts":[[2024,9,1]]}}}