{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T10:21:58Z","timestamp":1775470918488,"version":"3.50.1"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,9,1]]},"DOI":"10.1109\/vdat63601.2024.10705738","type":"proceedings-article","created":{"date-parts":[[2024,10,9]],"date-time":"2024-10-09T17:45:58Z","timestamp":1728495958000},"page":"1-6","source":"Crossref","is-referenced-by-count":3,"title":["A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications"],"prefix":"10.1109","author":[{"given":"Venkata Reddy","family":"Kolagatla","sequence":"first","affiliation":[{"name":"C-DAC,ChipIN Centre,Bangalore"}]},{"given":"Aneesh","family":"Raveendran","sequence":"additional","affiliation":[{"name":"C-DAC,ChipIN Centre,Bangalore"}]},{"given":"Vivian","family":"Desalphine","sequence":"additional","affiliation":[{"name":"C-DAC,ChipIN Centre,Bangalore"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/359340.359342"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2020.04.087"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1504\/IJHPSA.2007.013290"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2008.13"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-71817-0_10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICASIC.2003.1277455"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2005.863188"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329328"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2458033"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICM.2016.7847871"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCC.2012.202"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2020.01.024"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-014-5215-4"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2004.1354396"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000524"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT53777.2021.9601132"},{"key":"ref17","first-page":"800","article-title":"A Low Latency Montgomery Modular Exponentiation","volume-title":"Proc. Comp. Sc","volume":"171","author":"Kolagatla"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VDAT53777.2021.9601001"}],"event":{"name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","location":"Vellore, India","start":{"date-parts":[[2024,9,1]]},"end":{"date-parts":[[2024,9,3]]}},"container-title":["2024 28th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10705646\/10705432\/10705738.pdf?arnumber=10705738","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T14:46:16Z","timestamp":1728571576000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10705738\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,1]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/vdat63601.2024.10705738","relation":{},"subject":[],"published":{"date-parts":[[2024,9,1]]}}}