{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,30]],"date-time":"2025-05-30T06:09:53Z","timestamp":1748585393194},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,9,1]]},"DOI":"10.1109\/vdat63601.2024.10705740","type":"proceedings-article","created":{"date-parts":[[2024,10,9]],"date-time":"2024-10-09T17:45:58Z","timestamp":1728495958000},"page":"1-5","source":"Crossref","is-referenced-by-count":1,"title":[">Optimization of CMOS compatible non-perovskite ferroelectric gate stack for designing low power Ferroelectric tunnel FETs"],"prefix":"10.1109","author":[{"given":"Venkata Apparao","family":"Yempada","sequence":"first","affiliation":[{"name":"IIIT Hyderabad,CVEST,Telangana,India"}]},{"given":"Srivatsava","family":"Jandhyala","sequence":"additional","affiliation":[{"name":"IIIT Hyderabad,CVEST,Telangana,India"}]},{"given":"Janamani Chandram","family":"Ayyangalam","sequence":"additional","affiliation":[{"name":"GITAM School of Technology,Department of EECE,Visakhapatnam,India"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/VLSIT.2010.5556195"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/LED.2010.2044012"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TED.2007.899389"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1186\/s11671-017-1958-3"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/TED.2016.2604001"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/LED.2009.2021079"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1021\/nl071804g"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1063\/5.0037617"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TED.2010.2079531"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1016\/j.sse.2016.07.025"},{"year":"2007","journal-title":"Silvaco International Atlas user\u2019s manual","key":"ref11"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ESSDERC.2011.6044215"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1016\/j.mssp.2017.07.014"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/LED.2017.2734943"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1016\/j.sse.2014.12.002"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/TED.2015.2407695"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1016\/j.sse.2008.04.003"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/TED.2014.2329372"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1007\/s12633-021-01428-2"}],"event":{"name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","start":{"date-parts":[[2024,9,1]]},"location":"Vellore, India","end":{"date-parts":[[2024,9,3]]}},"container-title":["2024 28th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10705646\/10705432\/10705740.pdf?arnumber=10705740","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T11:22:06Z","timestamp":1728559326000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10705740\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,1]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/vdat63601.2024.10705740","relation":{},"subject":[],"published":{"date-parts":[[2024,9,1]]}}}