{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,17]],"date-time":"2026-04-17T16:30:30Z","timestamp":1776443430102,"version":"3.51.2"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,9,1]]},"DOI":"10.1109\/vdat63601.2024.10705748","type":"proceedings-article","created":{"date-parts":[[2024,10,9]],"date-time":"2024-10-09T17:45:58Z","timestamp":1728495958000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Low Latency VLSI Architecture of Histogram Equalization of Images"],"prefix":"10.1109","author":[{"given":"Mohamed Asan","family":"Basiri M","sequence":"first","affiliation":[{"name":"IIITDM,Department of Electronics and Communication Engineering,Kurnool,India,518007"}]}],"member":"263","reference":[{"key":"ref1","first-page":"319","article-title":"Efficient FPGA Implementations of Lifting based DWT with Partial Reconfiguration","volume-title":"Proc. IEEE International Conference on VLSI Design","author":"Basiri M"},{"key":"ref2","first-page":"119","volume-title":"Digital Image Processing","author":"Gonzalez","year":"2018"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/NSS\/MIC42677.2020.9508087"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.1995.529042"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1117\/12.319719"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2016.7577362"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/IACC.2016.148"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2011.6131111"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCE.2019.2900541"},{"key":"ref10","first-page":"63","article-title":"FPGA Implementation of Parallel Histogram Computation","volume-title":"Proc. HiPEAC Workshop on Reconfigurable Computing","author":"Shahbahrami"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2016.07.193"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2022.3169760"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1006\/rtim.1998.0134"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.3010634"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICEEE54059.2021.9718837"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2007.4295260"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s11554-011-0204-y"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/SPIN.2014.6777005"},{"key":"ref19","first-page":"335","volume-title":"Computer Organization ane Embedded Systems","author":"Harmacher","year":"2002"}],"event":{"name":"2024 28th International Symposium on VLSI Design and Test (VDAT)","location":"Vellore, India","start":{"date-parts":[[2024,9,1]]},"end":{"date-parts":[[2024,9,3]]}},"container-title":["2024 28th International Symposium on VLSI Design and Test (VDAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10705646\/10705432\/10705748.pdf?arnumber=10705748","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,10]],"date-time":"2024-10-10T17:21:35Z","timestamp":1728580895000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10705748\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9,1]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/vdat63601.2024.10705748","relation":{},"subject":[],"published":{"date-parts":[[2024,9,1]]}}}