{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T13:35:33Z","timestamp":1725543333286},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,4]]},"DOI":"10.1109\/vldi-dat.2013.6533844","type":"proceedings-article","created":{"date-parts":[[2013,6,26]],"date-time":"2013-06-26T17:24:15Z","timestamp":1372267455000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["A novel processor design flow using processor description language applied to a vector coprocessor"],"prefix":"10.1109","author":[{"given":"Makiko","family":"Ito","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Tomono","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yi Ge","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y.","family":"Takebe","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Toichi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Mouri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y.","family":"Hirose","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"3"},{"journal-title":"Processor Description Languages Applications and Methodologies","year":"2008","author":"mishra","key":"2"},{"journal-title":"3GPP TS 21 101 Technical Specification and Technical Reports for A UTRAN-based 3GPP System","year":"0","key":"1"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISOCC.2011.6138743"},{"key":"4","first-page":"1","article-title":"ASIC synthesis using architecture description language","author":"wang","year":"2012","journal-title":"Proc Int Symp VLSI Design Automat Test (VLSI-DAT)"}],"event":{"name":"2013 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)","start":{"date-parts":[[2013,4,22]]},"location":"Hsinchu","end":{"date-parts":[[2013,4,24]]}},"container-title":["2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6526674\/6533796\/06533844.pdf?arnumber=6533844","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T18:50:33Z","timestamp":1490208633000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6533844\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,4]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/vldi-dat.2013.6533844","relation":{},"subject":[],"published":{"date-parts":[[2013,4]]}}}